| /trunk/kernel/arch/sparc64/include/interrupt.h |
|---|
| 43,9 → 43,14 |
| #define IVT_ITEMS 15 |
| #define IVT_FIRST 1 |
| /* This needs to be defined for inter-architecture API portability. */ |
| #define VECTOR_TLB_SHOOTDOWN_IPI 0 |
| #define IPI_TLB_SHOOTDOWN VECTOR_TLB_SHOOTDOWN_IPI |
| enum { |
| IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI, |
| IPI_DCACHE_SHOOTDOWN |
| }; |
| struct istate { |
| uint64_t tnpc; |
| uint64_t tpc; |
| /trunk/kernel/arch/sparc64/include/mm/as.h |
|---|
| 52,7 → 52,7 |
| #ifdef CONFIG_TSB |
| tsb_entry_t *itsb; |
| tsb_entry_t *dtsb; |
| #endif |
| #endif /* CONFIG_TSB */ |
| } as_arch_t; |
| #ifdef CONFIG_TSB |
| /trunk/kernel/arch/sparc64/include/mm/cache.h |
|---|
| 35,6 → 35,16 |
| #ifndef KERN_sparc64_CACHE_H_ |
| #define KERN_sparc64_CACHE_H_ |
| #ifdef CONFIG_SMP |
| extern void dcache_shootdown_start(void); |
| extern void dcache_shootdown_finalize(void); |
| extern void dcache_shootdown_ipi_recv(void); |
| #else /* CONFIG_SMP */ |
| #define dcache_shootdown_start(); |
| #define dcache_shootdown_finalize(); |
| #define dcache_shootdown_ipi_recv(); |
| #endif /* CONFIG_SMP */ |
| extern void dcache_flush(void); |
| #endif |
| /trunk/kernel/arch/sparc64/include/cpu.h |
|---|
| 55,6 → 55,7 |
| uint32_t mid; /**< Processor ID as read from UPA_CONFIG. */ |
| ver_reg_t ver; |
| uint32_t clock_frequency; /**< Processor frequency in MHz. */ |
| int dcache_active; /**< When non-zero, the D-cache is not being shot down. */ |
| }; |
| #endif |