| /trunk/kernel/arch/sparc64/include/regdef.h |
|---|
| 43,10 → 43,12 |
| #define PSTATE_MG_BIT (1<<10) |
| #define PSTATE_PRIV_BIT (1<<2) |
| #define PSTATE_PEF_BIT (1<<4) |
| #define TSTATE_PSTATE_SHIFT 8 |
| #define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT<<TSTATE_PSTATE_SHIFT) |
| #define TSTATE_IE_BIT (PSTATE_IE_BIT<<TSTATE_PSTATE_SHIFT) |
| #define TSTATE_PEF_BIT (PSTATE_PEF_BIT<<TSTATE_PSTATE_SHIFT) |
| #define TSTATE_CWP_MASK 0x1f |
| /trunk/kernel/arch/sparc64/include/fpu_context.h |
|---|
| 37,7 → 37,12 |
| #include <arch/types.h> |
| #define ARCH_HAS_FPU |
| #define FPU_CONTEXT_ALIGN 8 |
| struct fpu_context { |
| uint64_t d[32]; |
| uint64_t fsr; |
| }; |
| #endif |
| /trunk/kernel/arch/sparc64/include/asm.h |
|---|
| 108,6 → 108,28 |
| __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
| } |
| /** Read FPRS Register. |
| * |
| * @return Value of FPRS register. |
| */ |
| static inline uint64_t fprs_read(void) |
| { |
| uint64_t v; |
| __asm__ volatile ("rd %%fprs, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Write FPRS Register. |
| * |
| * @param v New value of FPRS register. |
| */ |
| static inline void fprs_write(uint64_t v) |
| { |
| __asm__ volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
| } |
| /** Read SOFTINT Register. |
| * |
| * @return Value of SOFTINT register. |
| /trunk/kernel/arch/sparc64/include/trap/exception.h |
|---|
| 40,6 → 40,7 |
| #define TT_INSTRUCTION_ACCESS_ERROR 0x0a |
| #define TT_ILLEGAL_INSTRUCTION 0x10 |
| #define TT_PRIVILEGED_OPCODE 0x11 |
| #define TT_FP_DISABLED 0x20 |
| #define TT_DIVISION_BY_ZERO 0x28 |
| #define TT_DATA_ACCESS_EXCEPTION 0x30 |
| #define TT_DATA_ACCESS_ERROR 0x32 |
| 56,6 → 57,7 |
| extern void instruction_access_error(int n, istate_t *istate); |
| extern void illegal_instruction(int n, istate_t *istate); |
| extern void privileged_opcode(int n, istate_t *istate); |
| extern void fp_disabled(int n, istate_t *istate); |
| extern void division_by_zero(int n, istate_t *istate); |
| extern void data_access_exception(int n, istate_t *istate); |
| extern void data_access_error(int n, istate_t *istate); |
| /trunk/kernel/arch/sparc64/include/register.h |
|---|
| 87,7 → 87,7 |
| union tick_compare_reg { |
| uint64_t value; |
| struct { |
| unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */ |
| unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */ |
| uint64_t tick_cmpr : 63; /**< Compare value for TICK interrupts. */ |
| } __attribute__ ((packed)); |
| }; |
| 105,6 → 105,18 |
| }; |
| typedef union softint_reg softint_reg_t; |
| /** Floating-point Registers State Register. */ |
| union fprs_reg { |
| uint64_t value; |
| struct { |
| uint64_t : 61; |
| unsigned fef : 1; |
| unsigned du : 1; |
| unsigned dl : 1; |
| } __attribute__ ((packed)); |
| }; |
| typedef union fprs_reg fprs_reg_t; |
| #endif |
| /** @} |