| /trunk/kernel/arch/sparc64/include/arch.h |
|---|
| 29,7 → 29,9 |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| /** |
| * @file |
| * @brief Various sparc64-specific macros. |
| */ |
| #ifndef __sparc64_ARCH_H__ |
| 38,8 → 40,9 |
| #define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ |
| #define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ |
| #define NWINDOW 8 /** Number of register window sets. */ |
| #endif |
| /** @} |
| */ |
| /trunk/kernel/arch/sparc64/include/proc/thread.h |
|---|
| 26,22 → 26,24 |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64proc |
| /** @addtogroup sparc64proc |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef __sparc64_THREAD_H__ |
| #define __sparc64_THREAD_H__ |
| #ifndef KERN_sparc64_THREAD_H_ |
| #define KERN_sparc64_THREAD_H_ |
| #include <arch/types.h> |
| #include <arch/arch.h> |
| typedef struct { |
| /** Buffer for register windows with userspace content. */ |
| uint8_t *uspace_window_buffer; |
| } thread_arch_t; |
| #define thread_create_arch(t) |
| #endif |
| /** @} |
| /** @} |
| */ |
| /trunk/kernel/arch/sparc64/include/trap/regwin.h |
|---|
| 50,8 → 50,6 |
| #define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE |
| #define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE |
| #define NWINDOW 8 |
| /* Window Save Area offsets. */ |
| #define L0_OFFSET 0 |
| #define L1_OFFSET 8 |
| 249,4 → 247,3 |
| /** @} |
| */ |
| /trunk/kernel/arch/sparc64/include/barrier.h |
|---|
| 51,10 → 51,14 |
| /* |
| * The FLUSH instruction takes address parameter. |
| * As such, it may trap if the address is not found in DTLB. |
| * However, JPS1 implementations are free to ignore the trap. |
| * |
| * The entire kernel text is mapped by a locked ITLB and |
| * DTLB entries. Therefore, when this function is called, |
| * the %o7 register will always be in the range mapped by |
| * DTLB. |
| */ |
| __asm__ volatile ("flush %0\n" :: "r" (0x400000)); |
| __asm__ volatile ("flush %o7\n"); |
| } |
| /** Memory Barrier instruction. */ |