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Ignore whitespace Rev 1851 → Rev 1852

/trunk/kernel/arch/sparc64/include/interrupt.h
44,13 → 44,6
#define IVT_ITEMS 15
#define IVT_FIRST 1
 
/* Dummy macros. */
#define IRQ_KBD 2
#define VECTOR_KBD IRQ_KBD
 
#define trap_virtual_enable_irqs(x)
#define trap_virtual_eoi()
 
struct istate {
uint64_t pstate;
uint64_t tnpc;
/trunk/kernel/arch/sparc64/include/regdef.h
35,13 → 35,20
#ifndef KERN_sparc64_REGDEF_H_
#define KERN_sparc64_REGDEF_H_
 
#define PSTATE_IE_BIT 2
#define PSTATE_AM_BIT 8
#define PSTATE_IE_BIT (1<<1)
#define PSTATE_AM_BIT (1<<3)
 
#define PSTATE_AG_BIT (1<<0)
#define PSTATE_IG_BIT (1<<11)
#define PSTATE_MG_BIT (1<<10)
 
#define PSTATE_PRIV_BIT (1<<2)
 
#define TSTATE_PSTATE_SHIFT 8
#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT<<TSTATE_PSTATE_SHIFT)
 
#define TSTATE_CWP_MASK 0x1f
 
#endif
 
/** @}
/trunk/kernel/arch/sparc64/include/arch.h
35,6 → 35,9
#ifndef __sparc64_ARCH_H__
#define __sparc64_ARCH_H__
 
#define ASI_AIUP 0x10 /** Access to primary context with user privileges. */
#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */
 
#endif
 
/** @}
/trunk/kernel/arch/sparc64/include/trap/regwin.h
38,6 → 38,7
#define __sparc64_REGWIN_H__
 
#include <arch/stack.h>
#include <arch/arch.h>
 
#define TT_CLEAN_WINDOW 0x24
#define TT_SPILL_0_NORMAL 0x80
49,7 → 50,9
#define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
#define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
 
/** Window Save Area offsets. */
#define NWINDOW 8
 
/* Window Save Area offsets. */
#define L0_OFFSET 0
#define L1_OFFSET 8
#define L2_OFFSET 16
68,7 → 71,11
#define I7_OFFSET 120
 
#ifdef __ASM__
.macro SPILL_NORMAL_HANDLER
 
/*
* Macro used by the nucleus and the primary context 0 during normal and other spills.
*/
.macro SPILL_NORMAL_HANDLER_KERNEL
stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
89,7 → 96,61
retry
.endm
 
.macro FILL_NORMAL_HANDLER
/*
* Macro used by the userspace during normal spills.
*/
.macro SPILL_NORMAL_HANDLER_USERSPACE
wr ASI_AIUP, %asi
stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi
stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi
stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi
stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi
stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi
stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi
stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi
stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi
stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi
stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi
stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi
stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi
stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi
stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi
stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi
stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi
saved
retry
.endm
 
/*
* Macro used by the userspace during other spills.
*/
.macro SPILL_OTHER_HANDLER_USERSPACE
wr ASI_AIUS, %asi
stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi
stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi
stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi
stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi
stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi
stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi
stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi
stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi
stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi
stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi
stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi
stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi
stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi
stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi
stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi
stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi
saved
retry
.endm
 
 
/*
* Macro used by the nucleus and the primary context 0 during normal fills.
*/
.macro FILL_NORMAL_HANDLER_KERNEL
ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
ldx [%sp + STACK_BIAS + L2_OFFSET], %l2
110,6 → 171,56
retry
.endm
 
/*
* Macro used by the userspace during normal fills.
*/
.macro FILL_NORMAL_HANDLER_USERSPACE
wr ASI_AIUP, %asi
ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0
ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1
ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2
ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3
ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4
ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5
ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6
ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7
ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0
ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1
ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2
ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3
ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4
ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5
ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6
ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7
restored
retry
.endm
 
/*
* Macro used by the userspace during other fills.
*/
.macro FILL_OTHER_HANDLER_USERSPACE
wr ASI_AIUS, %asi
ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0
ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1
ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2
ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3
ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4
ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5
ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6
ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7
ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0
ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1
ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2
ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3
ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4
ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5
ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6
ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7
restored
retry
.endm
 
.macro CLEAN_WINDOW_HANDLER
rdpr %cleanwin, %l0
add %l0, 1, %l0
/trunk/kernel/arch/sparc64/include/trap/interrupt.h
79,8 → 79,7
 
#ifdef __ASM__
.macro INTERRUPT_LEVEL_N_HANDLER n
save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
mov \n - 1, %o0
mov \n - 1, %g2
PREEMPTIBLE_HANDLER exc_dispatch
.endm
 
/trunk/kernel/arch/sparc64/include/trap/trap_table.h
85,12 → 85,11
#define SAVED_TSTATE -(1*8)
#define SAVED_TPC -(2*8)
#define SAVED_TNPC -(3*8)
#define SAVED_PSTATE -(4*8)
 
.macro PREEMPTIBLE_HANDLER f
set \f, %l0
sethi %hi(\f), %g1
b preemptible_handler
nop
or %g1, %lo(\f), %g1
.endm
 
.macro SIMPLE_HANDLER f
/trunk/kernel/arch/sparc64/include/trap/mmu.h
38,6 → 38,7
#define __sparc64_MMU_TRAP_H__
 
#include <arch/stack.h>
#include <arch/regdef.h>
#include <arch/mm/tlb.h>
#include <arch/mm/mmu.h>
#include <arch/mm/tte.h>
59,7 → 60,12
 
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
/*
* First, test if it is the portion of the kernel address space
* First, try to refill TLB from TSB.
*/
! TODO
 
/*
* Second, test if it is the portion of the kernel address space
* which is faulting. If that is the case, immediately create
* identity mapping for that page in DTLB. VPN 0 is excluded from
* this treatment.
66,6 → 72,7
*
* Note that branch-delay slots are used in order to save space.
*/
0:
mov VA_DMMU_TAG_ACCESS, %g1
ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN
set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
74,11 → 81,6
andncc %g1, %g2, %g3 ! get page address into %g3
bz 0f ! page address is zero
 
/*
* Create and insert the identity-mapped entry for
* the faulting kernel page.
*/
or %g3, (TTE_CP|TTE_P|TTE_W), %g2 ! 8K pages are the default (encoded as 0)
set 1, %g3
sllx %g3, TTE_V_SHIFT, %g3
86,8 → 88,15
stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page
retry
 
/*
* Third, catch and handle special cases when the trap is caused by
* some register window trap handler.
*/
0:
save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
! TODO
 
0:
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
.endm