/trunk/kernel/arch/sparc64/include/asm.h |
---|
139,6 → 139,17 |
__asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
} |
/** Write SET_SOFTINT Register. |
* |
* Bits set in SET_SOFTINT register will be set in SOFTINT register. |
* |
* @param v New value of SET_SOFTINT register. |
*/ |
static inline void set_softint_write(uint64_t v) |
{ |
__asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
} |
/** Enable interrupts. |
* |
* Enable interrupts and return previous |
/trunk/kernel/arch/sparc64/include/trap/interrupt.h |
---|
40,6 → 40,22 |
#include <arch/trap/trap_table.h> |
#include <arch/stack.h> |
/* Interrupt ASI registers. */ |
#define ASI_UDB_INTR_W 0x77 |
#define ASI_INTR_DISPATCH_STATUS 0x48 |
#define ASI_UDB_INTR_R 0x7f |
#define ASI_INTR_RECEIVE 0x49 |
/* VA's used with ASI_UDB_INTR_W register. */ |
#define ASI_UDB_INTR_W_DATA_0 0x40 |
#define ASI_UDB_INTR_W_DATA_1 0x50 |
#define ASI_UDB_INTR_W_DATA_2 0x60 |
/* VA's used with ASI_UDB_INTR_R register. */ |
#define ASI_UDB_INTR_R_DATA_0 0x40 |
#define ASI_UDB_INTR_R_DATA_1 0x50 |
#define ASI_UDB_INTR_R_DATA_2 0x60 |
#define TT_INTERRUPT_LEVEL_1 0x41 |
#define TT_INTERRUPT_LEVEL_2 0x42 |
#define TT_INTERRUPT_LEVEL_3 0x43 |
70,10 → 86,17 |
.endm |
.macro INTERRUPT_VECTOR_TRAP_HANDLER |
save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
SIMPLE_HANDLER interrupt |
restore |
retry |
.endm |
#endif /* __ASM__ */ |
#ifndef __ASM__ |
extern void interrupt(void); |
#endif /* !def __ASM__ */ |
#endif |
/** @} |
/trunk/kernel/arch/sparc64/include/mm/mmu.h |
---|
35,10 → 35,10 |
#ifndef __sparc64_MMU_H__ |
#define __sparc64_MMU_H__ |
/** LSU Control Register ASI. */ |
/* LSU Control Register ASI. */ |
#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ |
/** I-MMU ASIs. */ |
/* I-MMU ASIs. */ |
#define ASI_IMMU 0x50 |
#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
47,13 → 47,13 |
#define ASI_ITLB_TAG_READ_REG 0x56 |
#define ASI_IMMU_DEMAP 0x57 |
/** Virtual Addresses within ASI_IMMU. */ |
/* Virtual Addresses within ASI_IMMU. */ |
#define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
/** D-MMU ASIs. */ |
/* D-MMU ASIs. */ |
#define ASI_DMMU 0x58 |
#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
63,7 → 63,7 |
#define ASI_DTLB_TAG_READ_REG 0x5e |
#define ASI_DMMU_DEMAP 0x5f |
/** Virtual Addresses within ASI_DMMU. */ |
/* Virtual Addresses within ASI_DMMU. */ |
#define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
/trunk/kernel/arch/sparc64/include/drivers/z8530.h |
---|
70,6 → 70,9 |
#define RR14 14 |
#define RR15 15 |
/* Write Register 0 */ |
#define WR0_ERR_RST (0x6<<3) |
/* Write Register 1 */ |
#define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */ |
#define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */ |
/trunk/kernel/arch/sparc64/include/drivers/fhc.h |
---|
0,0 → 1,48 |
/* |
* Copyright (C) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_FHC_H_ |
#define KERN_sparc64_FHC_H_ |
#include <arch/types.h> |
extern volatile uint32_t *fhc; |
extern void fhc_init(void); |
extern void fhc_uart_reset(void); |
#endif |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/drivers/ns16550.h |
---|
39,6 → 39,7 |
#include <arch/drivers/kbd.h> |
#define RBR_REG 0 /** Receiver Buffer Register. */ |
#define IER_REG 1 /** Interrupt Enable Register. */ |
#define LSR_REG 5 /** Line Status Register. */ |
static inline uint8_t ns16550_rbr_read(void) |
46,6 → 47,16 |
return kbd_virt_address[RBR_REG]; |
} |
static inline uint8_t ns16550_ier_read(void) |
{ |
return kbd_virt_address[IER_REG]; |
} |
static inline void ns16550_ier_write(uint8_t v) |
{ |
kbd_virt_address[IER_REG] = v; |
} |
static inline uint8_t ns16550_lsr_read(void) |
{ |
return kbd_virt_address[LSR_REG]; |