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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /trunk/kernel/arch/sparc64/include/mm @ 1793

  → /trunk/kernel/arch/sparc64/include/mm @ 1822

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1793 → Rev 1822

/trunk/kernel/arch/sparc64/include/mm/page.h
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup sparc64mm
/** @addtogroup sparc64mm
* @{
*/
/** @file
65,6 → 65,5
#endif
/** @}
/** @}
*/

/trunk/kernel/arch/sparc64/include/mm/tte.h
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup sparc64mm
/** @addtogroup sparc64mm
* @{
*/
/** @file
77,6 → 77,5
#endif
/** @}
/** @}
*/

/trunk/kernel/arch/sparc64/include/mm/mmu.h
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup sparc64mm
/** @addtogroup sparc64mm
* @{
*/
/** @file
35,11 → 35,6
#ifndef __sparc64_MMU_H__
#define __sparc64_MMU_H__
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <typedefs.h>
/** LSU Control Register ASI. */
#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */
79,7 → 74,13
#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */
#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */
#ifndef __ASM__
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <typedefs.h>
/** LSU Control Register. */
union lsu_cr_reg {
uint64_t value;
102,36 → 103,9
};
typedef union lsu_cr_reg lsu_cr_reg_t;
#endif /* !__ASM__ */
#define immu_enable() immu_set(true)
#define immu_disable() immu_set(false)
#define dmmu_enable() dmmu_set(true)
#define dmmu_disable() dmmu_set(false)
/** Disable or Enable IMMU. */
static inline void immu_set(bool enable)
{
lsu_cr_reg_t cr;
cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
cr.im = enable;
asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
membar();
}
/** Disable or Enable DMMU. */
static inline void dmmu_set(bool enable)
{
lsu_cr_reg_t cr;
cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
cr.dm = enable;
asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
membar();
}
#endif
/** @}
/** @}
*/

/trunk/kernel/arch/sparc64/include/mm/tlb.h
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup sparc64mm
/** @addtogroup sparc64mm
* @{
*/
/** @file
227,7 → 227,7
reg.value = 0;
reg.tlb_entry = entry;
asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
flush();
membar();
}
/** Read IMMU TLB Tag Read Register.
286,7 → 286,7
static inline void dtlb_tag_access_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
flush();
membar();
}
/** Read DMMU TLB Tag Access Register.
316,7 → 316,7
static inline void dtlb_data_in_write(uint64_t v)
{
asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
flush();
membar();
}
/** Read ITLB Synchronous Fault Status Register.
354,7 → 354,7
static inline void dtlb_sfsr_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
flush();
membar();
}
/** Read DTLB Synchronous Fault Address Register.
407,7 → 407,7
da.vpn = pg.vpn;
asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
flush();
membar();
}
extern void fast_instruction_access_mmu_miss(void);
418,6 → 418,5
#endif
/** @}
/** @}
*/