| 66,6 → 66,7 |
|---|
| |
| /* TLB Tag Access shifts */ |
| #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
| #define TLB_TAG_ACCESS_CONTEXT_MASK ((1<<13)-1) |
| #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
| |
| #ifndef __ASM__ |
| 131,11 → 132,9 |
|---|
| union tlb_sfsr_reg { |
| uint64_t value; |
| struct { |
| unsigned long : 39; /**< Implementation dependent. */ |
| unsigned nf : 1; /**< Nonfaulting load. */ |
| unsigned long : 40; /**< Implementation dependent. */ |
| unsigned asi : 8; /**< ASI. */ |
| unsigned tm : 1; /**< TLB miss. */ |
| unsigned : 1; |
| unsigned : 2; |
| unsigned ft : 7; /**< Fault type. */ |
| unsigned e : 1; /**< Side-effect bit. */ |
| unsigned ct : 2; /**< Context Register selection. */ |
| 425,9 → 424,9 |
|---|
| membar(); |
| } |
| |
| extern void fast_instruction_access_mmu_miss(void); |
| extern void fast_data_access_mmu_miss(void); |
| extern void fast_data_access_protection(void); |
| extern void fast_instruction_access_mmu_miss(int n, istate_t *istate); |
| extern void fast_data_access_mmu_miss(int n, istate_t *istate); |
| extern void fast_data_access_protection(int n, istate_t *istate); |
| |
| extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
| |