35,11 → 35,6 |
#ifndef __sparc64_MMU_H__ |
#define __sparc64_MMU_H__ |
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#include <arch/asm.h> |
#include <arch/barrier.h> |
#include <arch/types.h> |
#include <typedefs.h> |
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/** LSU Control Register ASI. */ |
#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ |
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79,7 → 74,13 |
#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
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#ifndef __ASM__ |
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#include <arch/asm.h> |
#include <arch/barrier.h> |
#include <arch/types.h> |
#include <typedefs.h> |
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/** LSU Control Register. */ |
union lsu_cr_reg { |
uint64_t value; |
102,36 → 103,9 |
}; |
typedef union lsu_cr_reg lsu_cr_reg_t; |
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#endif /* !__ASM__ */ |
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#define immu_enable() immu_set(true) |
#define immu_disable() immu_set(false) |
#define dmmu_enable() dmmu_set(true) |
#define dmmu_disable() dmmu_set(false) |
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/** Disable or Enable IMMU. */ |
static inline void immu_set(bool enable) |
{ |
lsu_cr_reg_t cr; |
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cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0); |
cr.im = enable; |
asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value); |
membar(); |
} |
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/** Disable or Enable DMMU. */ |
static inline void dmmu_set(bool enable) |
{ |
lsu_cr_reg_t cr; |
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cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0); |
cr.dm = enable; |
asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value); |
membar(); |
} |
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#endif |
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/** @} |
*/ |
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