| /trunk/kernel/arch/sparc64/include/interrupt.h |
|---|
| 46,7 → 46,8 |
| #define VECTOR_TLB_SHOOTDOWN_IPI 0 |
| enum { |
| IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI |
| IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI, |
| IPI_DCACHE_SHOOTDOWN |
| }; |
| typedef struct { |
| /trunk/kernel/arch/sparc64/include/mm/cache.h |
|---|
| 43,10 → 43,44 |
| #define dcache_flush_frame(p, f) \ |
| dcache_flush_tag(PAGE_COLOR((p)), ADDR2PFN((f))); |
| /** |
| * Enumerations to differentiate among different scopes of D-Cache |
| * invalidation. |
| */ |
| typedef enum { |
| DCACHE_INVL_INVALID, |
| DCACHE_INVL_ALL, |
| DCACHE_INVL_COLOR, |
| DCACHE_INVL_FRAME |
| } dcache_invalidate_type_t; |
| /** |
| * Number of messages that can be queued in the cpu_arch_t structure at a time. |
| */ |
| #define DCACHE_MSG_QUEUE_LEN 10 |
| /** D-cache shootdown message type. */ |
| typedef struct { |
| dcache_invalidate_type_t type; |
| int color; |
| uintptr_t frame; |
| } dcache_shootdown_msg_t; |
| extern void dcache_flush(void); |
| extern void dcache_flush_color(int c); |
| extern void dcache_flush_tag(int c, pfn_t tag); |
| #ifdef CONFIG_SMP |
| extern void dcache_shootdown_start(dcache_invalidate_type_t type, int color, |
| uintptr_t frame); |
| extern void dcache_shootdown_finalize(void); |
| extern void dcache_shootdown_ipi_recv(void); |
| #else |
| #define dcache_shootdown_start(t, c, f) |
| #define dcache_shootdown_finalize() |
| #define dcache_shootdown_ipi_recv() |
| #endif /* CONFIG_SMP */ |
| #endif |
| /** @} |
| /trunk/kernel/arch/sparc64/include/cpu.h |
|---|
| 39,6 → 39,10 |
| #include <arch/register.h> |
| #include <arch/asm.h> |
| #ifdef CONFIG_SMP |
| #include <arch/mm/cache.h> |
| #endif |
| #define MANUF_FUJITSU 0x04 |
| #define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ |
| #define MANUF_SUN 0x3e |
| 53,12 → 57,18 |
| #define IMPL_SPARC64V 0x5 |
| typedef struct { |
| uint32_t mid; /**< Processor ID as read from UPA_CONFIG. */ |
| uint32_t mid; /**< Processor ID as read from |
| UPA_CONFIG. */ |
| ver_reg_t ver; |
| uint32_t clock_frequency; /**< Processor frequency in Hz. */ |
| uint64_t next_tick_cmpr; /**< Next clock interrupt should be |
| generated when the TICK register |
| matches this value. */ |
| generated when the TICK register |
| matches this value. */ |
| #ifdef CONFIG_SMP |
| int dcache_active; |
| dcache_shootdown_msg_t dcache_messages[DCACHE_MSG_QUEUE_LEN]; |
| count_t dcache_message_count; |
| #endif |
| } cpu_arch_t; |
| #endif |