/trunk/kernel/arch/sparc64/include/interrupt.h |
---|
40,11 → 40,13 |
#include <arch/types.h> |
#include <arch/regdef.h> |
#define IRQ_COUNT 1 /* TODO */ |
#define IRQ_COUNT 1 /* TODO */ |
#define IVT_ITEMS 15 |
#define IVT_FIRST 1 |
#define VECTOR_TLB_SHOOTDOWN_IPI 0 /* TODO */ |
struct istate { |
uint64_t tnpc; |
uint64_t tpc; |
/trunk/kernel/arch/sparc64/include/regdef.h |
---|
55,6 → 55,9 |
#define WSTATE_NORMAL(n) (n) |
#define WSTATE_OTHER(n) ((n)<<3) |
#define UPA_CONFIG_MID_SHIFT 17 |
#define UPA_CONFIG_MID_MASK 0x1f |
#endif |
/** @} |
/trunk/kernel/arch/sparc64/include/atomic.h |
---|
96,8 → 96,9 |
static inline long test_and_set(atomic_t *val) |
{ |
uint64_t v = 1; |
volatile uintptr_t x = (uint64_t) &val->count; |
__asm__ volatile ("casx %0, %2, %1\n" : "+m" (*val), "+r" (v) : "r" (0)); |
__asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0)); |
return v; |
} |
107,6 → 108,8 |
uint64_t tmp1 = 1; |
uint64_t tmp2; |
volatile uintptr_t x = (uint64_t) &val->count; |
__asm__ volatile ( |
"0:\n" |
"casx %0, %3, %1\n" |
119,7 → 122,7 |
"ba 1b\n" |
"nop\n" |
"2:\n" |
: "+m" (*val), "+r" (tmp1), "+r" (tmp2) : "r" (0) |
: "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0) |
); |
/* |
/trunk/kernel/arch/sparc64/include/cpu.h |
---|
35,6 → 35,7 |
#ifndef KERN_sparc64_CPU_H_ |
#define KERN_sparc64_CPU_H_ |
#include <arch/types.h> |
#include <arch/register.h> |
#define MANUF_FUJITSU 0x04 |
51,8 → 52,9 |
#define IMPL_SPARC64V 0x5 |
struct cpu_arch { |
uint32_t mid; /**< Processor ID as read from UPA_CONFIG. */ |
ver_reg_t ver; |
uint32_t clock_frequency; |
uint32_t clock_frequency; /**< Processor frequency in MHz. */ |
}; |
#endif |