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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /trunk/kernel/arch/sparc64/ @ 3133

  → /trunk/kernel/arch/sparc64 @ 3104

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 3133 → Rev 3104

/trunk/kernel/arch/sparc64/include/mm/cache_spec.h
File deleted

/trunk/kernel/arch/sparc64/include/mm/tlb.h
160,7 → 160,7
static inline void mmu_primary_context_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
flush_blind();
flush();
}
/** Read MMU Secondary Context Register.
179,7 → 179,7
static inline void mmu_secondary_context_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
flush_blind();
flush();
}
/** Read IMMU TLB Data Access Register.
209,7 → 209,7
reg.value = 0;
reg.tlb_entry = entry;
asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
flush_blind();
flush();
}
/** Read DMMU TLB Data Access Register.
279,7 → 279,7
static inline void itlb_tag_access_write(uint64_t v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
flush_blind();
flush();
}
/** Read IMMU TLB Tag Access Register.
318,7 → 318,7
static inline void itlb_data_in_write(uint64_t v)
{
asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
flush_blind();
flush();
}
/** Write DMMU TLB Data in Register.
347,7 → 347,7
static inline void itlb_sfsr_write(uint64_t v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
flush_blind();
flush();
}
/** Read DTLB Synchronous Fault Status Register.
400,7 → 400,7
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
* address within the
* ASI */
flush_blind();
flush();
}
/** Perform DMMU TLB Demap Operation.

/trunk/kernel/arch/sparc64/include/barrier.h
57,13 → 57,8
#define write_barrier() \
asm volatile ("membar #StoreStore\n" ::: "memory")
static inline void flush(uintptr_t addr)
{
asm volatile ("flush %0\n" :: "r" (addr) : "memory");
}
/** Flush Instruction Memory instruction. */
static inline void flush_blind(void)
static inline void flush(void)
{
/*
* The FLUSH instruction takes address parameter.
84,12 → 79,6
asm volatile ("membar #Sync\n");
}
#define smc_coherence(a) \
{ \
write_barrier(); \
flush((a)); \
}
#endif
/** @}

/trunk/kernel/arch/sparc64/src/mm/cache.S
27,8 → 27,10
*/
#include <arch/arch.h>
#include <arch/mm/cache_spec.h>
#define DCACHE_SIZE (16 * 1024)
#define DCACHE_LINE_SIZE 32
#define DCACHE_TAG_SHIFT 2
.register %g2, #scratch