/trunk/kernel/arch/sparc64/include/mm/tlb.h |
---|
382,7 → 382,8 |
/** Perform IMMU TLB Demap Operation. |
* |
* @param type Selects between context and page demap. |
* @param context_encoding Specifies which Context register has Context ID for demap. |
* @param context_encoding Specifies which Context register has Context ID for |
* demap. |
* @param page Address which is on the page to be demapped. |
*/ |
static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
397,7 → 398,9 |
da.context = context_encoding; |
da.vpn = pg.vpn; |
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
* address within the |
* ASI */ |
flush(); |
} |
404,7 → 407,8 |
/** Perform DMMU TLB Demap Operation. |
* |
* @param type Selects between context and page demap. |
* @param context_encoding Specifies which Context register has Context ID for demap. |
* @param context_encoding Specifies which Context register has Context ID for |
* demap. |
* @param page Address which is on the page to be demapped. |
*/ |
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
419,7 → 423,9 |
da.context = context_encoding; |
da.vpn = pg.vpn; |
asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
* address within the |
* ASI */ |
membar(); |
} |
/trunk/kernel/arch/sparc64/src/smp/ipi.c |
---|
73,10 → 73,13 |
panic("Interrupt Dispatch Status busy bit set\n"); |
do { |
asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func); |
asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) |
func); |
asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0); |
asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0); |
asi_u64_write(ASI_UDB_INTR_W, (mid << INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH, 0); |
asi_u64_write(ASI_UDB_INTR_W, (mid << |
INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH, |
0); |
membar(); |
/trunk/kernel/arch/sparc64/src/proc/scheduler.c |
---|
94,9 → 94,15 |
} |
/* |
* Write kernel stack address to %g6 and a pointer to the last |
* item in the userspace window buffer to %g7 in the alternate |
* and interrupt sets. |
* Write kernel stack address to %g6 of the alternate and |
* interrupt global sets. |
* |
* Write pointer to the last item in the userspace window buffer |
* to %g7 in the alternate set. Write to the interrupt %g7 is |
* not necessary because: |
* - spill traps operate only in the alternate global set, |
* - preemptible trap handler switches to alternate globals |
* before it explicitly uses %g7. |
*/ |
uint64_t sp = (uintptr_t) THREAD->kstack + STACK_SIZE |
- (STACK_BIAS + ALIGN_UP(STACK_ITEM_SIZE, |
109,7 → 115,7 |
/** Perform sparc64 specific steps before a thread stops running. |
* |
* Demap any locked DTLB entries isntalled by the thread (i.e. kernel stack |
* Demap any locked DTLB entries installed by the thread (i.e. kernel stack |
* and userspace window buffer). |
*/ |
void after_thread_ran_arch(void) |
/trunk/kernel/arch/sparc64/src/trap/interrupt.c |
---|
97,7 → 97,8 |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (intrcv=%#llx, data0=%#llx)\n", CPU->id, intrcv, data0); |
printf("cpu%d: spurious interrupt (intrcv=%#llx, " |
"data0=%#llx)\n", CPU->id, intrcv, data0); |
#endif |
} |