/trunk/kernel/arch/sparc64/include/drivers/z8530.h |
---|
91,42 → 91,48 |
/* Read Register 0 */ |
#define RR0_RCA (0x1<<0) /** Receive Character Available. */ |
static inline void z8530_write(index_t chan, uint8_t reg, uint8_t val) |
/** Structure representing the z8530 device. */ |
typedef struct { |
devno_t devno; |
volatile uint8_t *reg; /** Memory mapped registers of the z8530. */ |
} z8530_t; |
static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val) |
{ |
/* |
* Registers 8-15 will automatically issue the Point High |
* command as their bit 3 is 1. |
*/ |
kbd_virt_address[WR0+chan] = reg; /* select register */ |
kbd_virt_address[WR0+chan] = val; /* write value */ |
dev->reg[WR0+chan] = reg; /* select register */ |
dev->reg[WR0+chan] = val; /* write value */ |
} |
static inline void z8530_write_a(uint8_t reg, uint8_t val) |
static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val) |
{ |
z8530_write(Z8530_CHAN_A, reg, val); |
z8530_write(dev, Z8530_CHAN_A, reg, val); |
} |
static inline void z8530_write_b(uint8_t reg, uint8_t val) |
static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val) |
{ |
z8530_write(Z8530_CHAN_B, reg, val); |
z8530_write(dev, Z8530_CHAN_B, reg, val); |
} |
static inline uint8_t z8530_read(index_t chan, uint8_t reg) |
static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg) |
{ |
/* |
* Registers 8-15 will automatically issue the Point High |
* command as their bit 3 is 1. |
*/ |
kbd_virt_address[WR0+chan] = reg; /* select register */ |
return kbd_virt_address[WR0+chan]; |
dev->reg[WR0+chan] = reg; /* select register */ |
return dev->reg[WR0+chan]; |
} |
static inline uint8_t z8530_read_a(uint8_t reg) |
static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg) |
{ |
return z8530_read(Z8530_CHAN_A, reg); |
return z8530_read(dev, Z8530_CHAN_A, reg); |
} |
static inline uint8_t z8530_read_b(uint8_t reg) |
static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg) |
{ |
return z8530_read(Z8530_CHAN_B, reg); |
return z8530_read(dev, Z8530_CHAN_B, reg); |
} |
#endif |
/trunk/kernel/arch/sparc64/include/drivers/kbd.h |
---|
46,8 → 46,6 |
extern kbd_type_t kbd_type; |
extern volatile uint8_t *kbd_virt_address; |
extern void kbd_init(ofw_tree_node_t *node); |
#endif |
/trunk/kernel/arch/sparc64/include/drivers/ns16550.h |
---|
50,44 → 50,50 |
#define LCR_DLAB 0x80 /** Divisor Latch Access bit. */ |
static inline uint8_t ns16550_rbr_read(void) |
/** Structure representing the ns16550 device. */ |
typedef struct { |
devno_t devno; |
volatile uint8_t *reg; /** Memory mapped registers of the ns16550. */ |
} ns16550_t; |
static inline uint8_t ns16550_rbr_read(ns16550_t *dev) |
{ |
return kbd_virt_address[RBR_REG]; |
return dev->reg[RBR_REG]; |
} |
static inline uint8_t ns16550_ier_read(void) |
static inline uint8_t ns16550_ier_read(ns16550_t *dev) |
{ |
return kbd_virt_address[IER_REG]; |
return dev->reg[IER_REG]; |
} |
static inline void ns16550_ier_write(uint8_t v) |
static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v) |
{ |
kbd_virt_address[IER_REG] = v; |
dev->reg[IER_REG] = v; |
} |
static inline uint8_t ns16550_iir_read(void) |
static inline uint8_t ns16550_iir_read(ns16550_t *dev) |
{ |
return kbd_virt_address[IIR_REG]; |
return dev->reg[IIR_REG]; |
} |
static inline void ns16550_fcr_write(uint8_t v) |
static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v) |
{ |
kbd_virt_address[FCR_REG] = v; |
dev->reg[FCR_REG] = v; |
} |
static inline uint8_t ns16550_lcr_read(void) |
static inline uint8_t ns16550_lcr_read(ns16550_t *dev) |
{ |
return kbd_virt_address[LCR_REG]; |
return dev->reg[LCR_REG]; |
} |
static inline void ns16550_lcr_write(uint8_t v) |
static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v) |
{ |
kbd_virt_address[LCR_REG] = v; |
dev->reg[LCR_REG] = v; |
} |
static inline uint8_t ns16550_lsr_read(void) |
static inline uint8_t ns16550_lsr_read(ns16550_t *dev) |
{ |
return kbd_virt_address[LSR_REG]; |
return dev->reg[LSR_REG]; |
} |
#endif |
/trunk/kernel/arch/sparc64/src/drivers/kbd.c |
---|
49,12 → 49,8 |
#include <func.h> |
#include <print.h> |
volatile uint8_t *kbd_virt_address = NULL; |
kbd_type_t kbd_type = KBD_UNKNOWN; |
static irq_t kbd_irq; |
/** Initialize keyboard. |
* |
* Traverse OpenFirmware device tree in order to find necessary |
102,10 → 98,9 |
uintptr_t pa; |
size_t size; |
int inr; |
inr_t inr; |
devno_t devno = device_assign_devno(); |
irq_initialize(&kbd_irq); |
switch (kbd_type) { |
case KBD_Z8530: |
size = ((ofw_fhc_reg_t *) prop->value)->size; |
116,13 → 111,6 |
if (!ofw_fhc_map_interrupt(node->parent, ((ofw_fhc_reg_t *) prop->value), interrupts, &inr)) { |
printf("Failed to determine keyboard interrupt.\n"); |
return; |
} else { |
kbd_irq.inr = inr; |
kbd_irq.devno = device_assign_devno(); |
kbd_irq.trigger = IRQ_TRIGGER_LEVEL; |
kbd_irq.claim = z8530_claim; |
kbd_irq.handler = z8530_irq_handler; |
irq_register(&kbd_irq); |
} |
break; |
135,14 → 123,7 |
if (!ofw_ebus_map_interrupt(node->parent, ((ofw_ebus_reg_t *) prop->value), interrupts, &inr)) { |
printf("Failed to determine keyboard interrupt.\n"); |
return; |
} else { |
kbd_irq.inr = inr; |
kbd_irq.devno = device_assign_devno(); |
kbd_irq.trigger = IRQ_TRIGGER_LEVEL; |
kbd_irq.claim = ns16550_claim; |
kbd_irq.handler = ns16550_irq_handler; |
irq_register(&kbd_irq); |
} |
}; |
break; |
default: |
157,17 → 138,17 |
*/ |
aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE); |
offset = pa - aligned_addr; |
kbd_virt_address = (uint8_t *) hw_map(aligned_addr, offset + size) + offset; |
uintptr_t vaddr = hw_map(aligned_addr, offset + size) + offset; |
switch (kbd_type) { |
#ifdef CONFIG_Z8530 |
case KBD_Z8530: |
z8530_init(); |
z8530_init(devno, inr, vaddr); |
break; |
#endif |
#ifdef CONFIG_NS16550 |
case KBD_NS16550: |
ns16550_init(); |
ns16550_init(devno, inr, vaddr); |
break; |
#endif |
default: |