56,27 → 56,38 |
* Implementation of generic 4-level page table interface. |
* IA-32 has 2-level page tables, so PTL1 and PTL2 are left out. |
*/ |
|
/* Number of entries in each level. */ |
#define PTL0_ENTRIES_ARCH 1024 |
#define PTL1_ENTRIES_ARCH 0 |
#define PTL2_ENTRIES_ARCH 0 |
#define PTL3_ENTRIES_ARCH 1024 |
|
#define PTL0_SIZE_ARCH ONE_FRAME |
#define PTL1_SIZE_ARCH 0 |
#define PTL2_SIZE_ARCH 0 |
#define PTL3_SIZE_ARCH ONE_FRAME |
/* Page table size for each level. */ |
#define PTL0_SIZE_ARCH ONE_FRAME |
#define PTL1_SIZE_ARCH 0 |
#define PTL2_SIZE_ARCH 0 |
#define PTL3_SIZE_ARCH ONE_FRAME |
|
/* Macros calculating indices into page tables in each level. */ |
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) |
#define PTL1_INDEX_ARCH(vaddr) 0 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff) |
|
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12)) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12)) |
/* Get PTE address accessors for each level. */ |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12)) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
(ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
(ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12)) |
|
#define SET_PTL0_ADDRESS_ARCH(ptl0) { \ |
/* Set PTE address accessors for each level. */ |
#define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
{ \ |
mmuext_op_t mmu_ext; \ |
\ |
mmu_ext.cmd = MMUEXT_NEW_BASEPTR; \ |
84,7 → 95,8 |
ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \ |
} |
|
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \ |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
{ \ |
mmuext_op_t mmu_ext; \ |
\ |
mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; \ |
100,7 → 112,8 |
|
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) { \ |
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
{ \ |
mmu_update_t update; \ |
\ |
update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl3))[(i)])); \ |
108,21 → 121,35 |
ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \ |
} |
|
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *) (ptl0), (index_t)(i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *) (ptl3), (index_t)(i)) |
/* Get PTE flags accessors for each level. */ |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
get_pt_flags((pte_t *) (ptl0), (index_t) (i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
get_pt_flags((pte_t *) (ptl3), (index_t) (i)) |
|
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *) (ptl0), (index_t)(i), (x)) |
/* Set PTE flags accessors for each level. */ |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *) (ptl3), (index_t)(i), (x)) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) |
|
#define PTE_VALID_ARCH(p) (*((uint32_t *) (p)) != 0) |
#define PTE_PRESENT_ARCH(p) ((p)->present != 0) |
#define PTE_GET_FRAME_ARCH(p) ((p)->frame_address << FRAME_WIDTH) |
#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0) |
#define PTE_EXECUTABLE_ARCH(p) 1 |
/* Query macros for the last level. */ |
#define PTE_VALID_ARCH(p) \ |
(*((uint32_t *) (p)) != 0) |
#define PTE_PRESENT_ARCH(p) \ |
((p)->present != 0) |
#define PTE_GET_FRAME_ARCH(p) \ |
((p)->frame_address << FRAME_WIDTH) |
#define PTE_WRITABLE_ARCH(p) \ |
((p)->writeable != 0) |
#define PTE_EXECUTABLE_ARCH(p) \ |
1 |
|
#ifndef __ASM__ |
|
132,7 → 159,9 |
|
/* Page fault error codes. */ |
|
/** When bit on this position is 0, the page fault was caused by a not-present page. */ |
/** When bit on this position is 0, the page fault was caused by a not-present |
* page. |
*/ |
#define PFERR_CODE_P (1 << 0) |
|
/** When bit on this position is 1, the page fault was caused by a write. */ |
164,17 → 193,20 |
}; |
} mmuext_op_t; |
|
static inline int xen_update_va_mapping(const void *va, const pte_t pte, const unsigned int flags) |
static inline int xen_update_va_mapping(const void *va, const pte_t pte, |
const unsigned int flags) |
{ |
return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags); |
} |
|
static inline int xen_mmu_update(const mmu_update_t *req, const unsigned int count, unsigned int *success_count, domid_t domid) |
static inline int xen_mmu_update(const mmu_update_t *req, |
const unsigned int count, unsigned int *success_count, domid_t domid) |
{ |
return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid); |
} |
|
static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count, unsigned int *success_count, domid_t domid) |
static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count, |
unsigned int *success_count, domid_t domid) |
{ |
return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid); |
} |
183,15 → 215,13 |
{ |
pte_t *p = &pt[i]; |
|
return ( |
(!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT | |
(!p->present)<<PAGE_PRESENT_SHIFT | |
p->uaccessible<<PAGE_USER_SHIFT | |
1<<PAGE_READ_SHIFT | |
p->writeable<<PAGE_WRITE_SHIFT | |
1<<PAGE_EXEC_SHIFT | |
p->global<<PAGE_GLOBAL_SHIFT |
); |
return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | |
(!p->present) << PAGE_PRESENT_SHIFT | |
p->uaccessible << PAGE_USER_SHIFT | |
1 << PAGE_READ_SHIFT | |
p->writeable << PAGE_WRITE_SHIFT | |
1 << PAGE_EXEC_SHIFT | |
p->global << PAGE_GLOBAL_SHIFT); |
} |
|
static inline void set_pt_flags(pte_t *pt, index_t i, int flags) |