/trunk/kernel/arch/ia32/include/cpuid.h |
---|
76,7 → 76,7 |
{ |
uint32_t val, ret; |
__asm__ volatile ( |
asm volatile ( |
"pushf\n" /* read flags */ |
"popl %0\n" |
"movl %0, %1\n" |
99,7 → 99,7 |
static inline void cpuid(uint32_t cmd, cpu_info_t *info) |
{ |
__asm__ volatile ( |
asm volatile ( |
"movl %4, %%eax\n" |
"cpuid\n" |
/trunk/kernel/arch/ia32/include/memstr.h |
---|
51,7 → 51,7 |
{ |
unative_t d0, d1, d2; |
__asm__ __volatile__( |
asm volatile( |
/* copy all full dwords */ |
"rep movsl\n\t" |
/* load count again */ |
88,7 → 88,7 |
uint32_t d0, d1, d2; |
int ret; |
__asm__ ( |
asm ( |
"repe cmpsb\n\t" |
"je 1f\n\t" |
"movl %3, %0\n\t" |
114,7 → 114,7 |
{ |
uint32_t d0, d1; |
__asm__ __volatile__ ( |
asm volatile ( |
"rep stosw\n\t" |
: "=&D" (d0), "=&c" (d1), "=a" (x) |
: "0" (dst), "1" (cnt), "2" (x) |
136,7 → 136,7 |
{ |
uint32_t d0, d1; |
__asm__ __volatile__ ( |
asm volatile ( |
"rep stosb\n\t" |
: "=&D" (d0), "=&c" (d1), "=a" (x) |
: "0" (dst), "1" (cnt), "2" (x) |
/trunk/kernel/arch/ia32/include/atomic.h |
---|
42,17 → 42,17 |
static inline void atomic_inc(atomic_t *val) { |
#ifdef CONFIG_SMP |
__asm__ volatile ("lock incl %0\n" : "=m" (val->count)); |
asm volatile ("lock incl %0\n" : "=m" (val->count)); |
#else |
__asm__ volatile ("incl %0\n" : "=m" (val->count)); |
asm volatile ("incl %0\n" : "=m" (val->count)); |
#endif /* CONFIG_SMP */ |
} |
static inline void atomic_dec(atomic_t *val) { |
#ifdef CONFIG_SMP |
__asm__ volatile ("lock decl %0\n" : "=m" (val->count)); |
asm volatile ("lock decl %0\n" : "=m" (val->count)); |
#else |
__asm__ volatile ("decl %0\n" : "=m" (val->count)); |
asm volatile ("decl %0\n" : "=m" (val->count)); |
#endif /* CONFIG_SMP */ |
} |
60,7 → 60,7 |
{ |
long r = 1; |
__asm__ volatile ( |
asm volatile ( |
"lock xaddl %1, %0\n" |
: "=m" (val->count), "+r" (r) |
); |
72,7 → 72,7 |
{ |
long r = -1; |
__asm__ volatile ( |
asm volatile ( |
"lock xaddl %1, %0\n" |
: "=m" (val->count), "+r"(r) |
); |
86,7 → 86,7 |
static inline uint32_t test_and_set(atomic_t *val) { |
uint32_t v; |
__asm__ volatile ( |
asm volatile ( |
"movl $1, %0\n" |
"xchgl %0, %1\n" |
: "=r" (v),"=m" (val->count) |
101,7 → 101,7 |
uint32_t tmp; |
preemption_disable(); |
__asm__ volatile ( |
asm volatile ( |
"0:;" |
#ifdef CONFIG_HT |
"pause;" /* Pentium 4's HT love this instruction */ |
/trunk/kernel/arch/ia32/include/asm.h |
---|
57,19 → 57,26 |
* |
* Halt the current CPU until interrupt event. |
*/ |
static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
static inline void cpu_halt(void) |
{ |
asm("hlt\n"); |
}; |
static inline void cpu_sleep(void) |
{ |
asm("hlt\n"); |
}; |
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
{ \ |
unative_t res; \ |
__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
return res; \ |
} |
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
{ \ |
__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
asm volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
} |
GEN_READ_REG(cr0); |
98,7 → 105,10 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
static inline void outb(uint16_t port, uint8_t val) |
{ |
asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); |
} |
/** Word to port |
* |
107,7 → 117,10 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
static inline void outw(uint16_t port, uint16_t val) |
{ |
asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); |
} |
/** Double word to port |
* |
116,7 → 129,10 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
static inline void outl(uint16_t port, uint32_t val) |
{ |
asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); |
} |
/** Byte from port |
* |
125,8 → 141,14 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
static inline uint8_t inb(uint16_t port) |
{ |
uint8_t val; |
asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); |
return val; |
} |
/** Word from port |
* |
* Get word from port |
134,8 → 156,14 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
static inline uint16_t inw(uint16_t port) |
{ |
uint16_t val; |
asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); |
return val; |
} |
/** Double word from port |
* |
* Get double word from port |
143,8 → 171,14 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
static inline uint32_t inl(uint16_t port) |
{ |
uint32_t val; |
asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); |
return val; |
} |
/** Enable interrupts. |
* |
* Enable interrupts and return previous |
155,7 → 189,7 |
static inline ipl_t interrupts_enable(void) |
{ |
ipl_t v; |
__asm__ volatile ( |
asm volatile ( |
"pushf\n\t" |
"popl %0\n\t" |
"sti\n" |
174,7 → 208,7 |
static inline ipl_t interrupts_disable(void) |
{ |
ipl_t v; |
__asm__ volatile ( |
asm volatile ( |
"pushf\n\t" |
"popl %0\n\t" |
"cli\n" |
191,7 → 225,7 |
*/ |
static inline void interrupts_restore(ipl_t ipl) |
{ |
__asm__ volatile ( |
asm volatile ( |
"pushl %0\n\t" |
"popf\n" |
: : "r" (ipl) |
205,7 → 239,7 |
static inline ipl_t interrupts_read(void) |
{ |
ipl_t v; |
__asm__ volatile ( |
asm volatile ( |
"pushf\n\t" |
"popl %0\n" |
: "=r" (v) |
223,7 → 257,7 |
{ |
uintptr_t v; |
__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
return v; |
} |
233,7 → 267,7 |
{ |
uintptr_t *ip; |
__asm__ volatile ( |
asm volatile ( |
"mov %%eip, %0" |
: "=r" (ip) |
); |
246,7 → 280,7 |
*/ |
static inline void invlpg(uintptr_t addr) |
{ |
__asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
} |
/** Load GDTR register from memory. |
255,7 → 289,7 |
*/ |
static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
{ |
__asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
} |
/** Store GDTR register to memory. |
264,7 → 298,7 |
*/ |
static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
{ |
__asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
} |
/** Load IDTR register from memory. |
273,7 → 307,7 |
*/ |
static inline void idtr_load(ptr_16_32_t *idtr_reg) |
{ |
__asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg)); |
asm volatile ("lidtl %0\n" : : "m" (*idtr_reg)); |
} |
/** Load TR from descriptor table. |
282,7 → 316,7 |
*/ |
static inline void tr_load(uint16_t sel) |
{ |
__asm__ volatile ("ltr %0" : : "r" (sel)); |
asm volatile ("ltr %0" : : "r" (sel)); |
} |
#endif |
/trunk/kernel/arch/ia32/include/barrier.h |
---|
46,12 → 46,12 |
* Provisions are made to prevent compiler from reordering instructions itself. |
*/ |
#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory") |
#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory") |
#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") |
#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") |
static inline void cpuid_serialization(void) |
{ |
__asm__ volatile ( |
asm volatile ( |
"xorl %%eax, %%eax\n" |
"cpuid\n" |
::: "eax", "ebx", "ecx", "edx", "memory" |
59,20 → 59,20 |
} |
#ifdef CONFIG_FENCES_P4 |
# define memory_barrier() __asm__ volatile ("mfence\n" ::: "memory") |
# define read_barrier() __asm__ volatile ("lfence\n" ::: "memory") |
# define memory_barrier() asm volatile ("mfence\n" ::: "memory") |
# define read_barrier() asm volatile ("lfence\n" ::: "memory") |
# ifdef CONFIG_WEAK_MEMORY |
# define write_barrier() __asm__ volatile ("sfence\n" ::: "memory") |
# define write_barrier() asm volatile ("sfence\n" ::: "memory") |
# else |
# define write_barrier() __asm__ volatile( "" ::: "memory"); |
# define write_barrier() asm volatile( "" ::: "memory"); |
# endif |
#elif CONFIG_FENCES_P3 |
# define memory_barrier() cpuid_serialization() |
# define read_barrier() cpuid_serialization() |
# ifdef CONFIG_WEAK_MEMORY |
# define write_barrier() __asm__ volatile ("sfence\n" ::: "memory") |
# define write_barrier() asm volatile ("sfence\n" ::: "memory") |
# else |
# define write_barrier() __asm__ volatile( "" ::: "memory"); |
# define write_barrier() asm volatile( "" ::: "memory"); |
# endif |
#else |
# define memory_barrier() cpuid_serialization() |
80,7 → 80,7 |
# ifdef CONFIG_WEAK_MEMORY |
# define write_barrier() cpuid_serialization() |
# else |
# define write_barrier() __asm__ volatile( "" ::: "memory"); |
# define write_barrier() asm volatile( "" ::: "memory"); |
# endif |
#endif |
/trunk/kernel/arch/ia32/src/fpu_context.c |
---|
43,7 → 43,7 |
static void fpu_context_f_save(fpu_context_t *fctx) |
{ |
__asm__ volatile ( |
asm volatile ( |
"fnsave %0" |
: "=m"(*fctx) |
); |
51,7 → 51,7 |
static void fpu_context_f_restore(fpu_context_t *fctx) |
{ |
__asm__ volatile ( |
asm volatile ( |
"frstor %0" |
: "=m"(*fctx) |
); |
59,7 → 59,7 |
static void fpu_context_fx_save(fpu_context_t *fctx) |
{ |
__asm__ volatile ( |
asm volatile ( |
"fxsave %0" |
: "=m"(*fctx) |
); |
67,7 → 67,7 |
static void fpu_context_fx_restore(fpu_context_t *fctx) |
{ |
__asm__ volatile ( |
asm volatile ( |
"fxrstor %0" |
: "=m"(*fctx) |
); |
103,7 → 103,7 |
void fpu_init() |
{ |
uint32_t help0 = 0, help1 = 0; |
__asm__ volatile ( |
asm volatile ( |
"fninit;\n" |
"stmxcsr %0\n" |
"mov %0,%1;\n" |
/trunk/kernel/arch/ia32/src/cpu/cpu.c |
---|
71,7 → 71,7 |
void fpu_disable(void) |
{ |
__asm__ volatile ( |
asm volatile ( |
"mov %%cr0,%%eax;" |
"or $8,%%eax;" |
"mov %%eax,%%cr0;" |
83,7 → 83,7 |
void fpu_enable(void) |
{ |
__asm__ volatile ( |
asm volatile ( |
"mov %%cr0,%%eax;" |
"and $0xffFFffF7,%%eax;" |
"mov %%eax,%%cr0;" |
/trunk/kernel/arch/ia32/src/pm.c |
---|
147,7 → 147,7 |
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
static void clean_IOPL_NT_flags(void) |
{ |
__asm__ volatile ( |
asm volatile ( |
"pushfl\n" |
"pop %%eax\n" |
"and $0xffff8fff, %%eax\n" |
160,7 → 160,7 |
/* Clean AM(18) flag in CR0 register */ |
static void clean_AM_flag(void) |
{ |
__asm__ volatile ( |
asm volatile ( |
"mov %%cr0, %%eax\n" |
"and $0xfffbffff, %%eax\n" |
"mov %%eax, %%cr0\n" |
/trunk/kernel/arch/ia32/src/userspace.c |
---|
51,7 → 51,7 |
ipl = interrupts_disable(); |
__asm__ volatile ( |
asm volatile ( |
/* |
* Clear nested task flag. |
*/ |