26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
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/** @addtogroup ia32 |
/** @addtogroup ia32 |
* @{ |
*/ |
/** @file |
39,10 → 39,8 |
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typedef void (*fpu_context_function)(fpu_context_t *fctx); |
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static fpu_context_function fpu_save,fpu_restore; |
static fpu_context_function fpu_save, fpu_restore; |
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static void fpu_context_f_save(fpu_context_t *fctx) |
{ |
__asm__ volatile ( |
88,12 → 86,10 |
*/ |
void fpu_fsr(void) |
{ |
fpu_save=fpu_context_f_save; |
fpu_restore=fpu_context_f_restore; |
fpu_save = fpu_context_f_save; |
fpu_restore = fpu_context_f_restore; |
} |
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void fpu_context_save(fpu_context_t *fctx) |
{ |
fpu_save(fctx); |
104,11 → 100,9 |
fpu_restore(fctx); |
} |
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void fpu_init() |
{ |
uint32_t help0=0,help1=0; |
uint32_t help0 = 0, help1 = 0; |
__asm__ volatile ( |
"fninit;\n" |
"stmxcsr %0\n" |
116,11 → 110,10 |
"or %2,%1;\n" |
"mov %1,%0;\n" |
"ldmxcsr %0;\n" |
:"+m"(help0),"+r"(help1) |
:"i"(0x1f80) |
: "+m" (help0), "+r" (help1) |
: "i" (0x1f80) |
); |
} |
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/** @} |
/** @} |
*/ |
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