| /trunk/kernel/arch/ia32/src/fpu_context.c |
|---|
| 43,7 → 43,7 |
|---|
| |
| static void fpu_context_f_save(fpu_context_t *fctx) |
| { |
| __asm__ volatile ( |
| asm volatile ( |
| "fnsave %0" |
| : "=m"(*fctx) |
| ); |
| 51,7 → 51,7 |
|---|
| |
| static void fpu_context_f_restore(fpu_context_t *fctx) |
| { |
| __asm__ volatile ( |
| asm volatile ( |
| "frstor %0" |
| : "=m"(*fctx) |
| ); |
| 59,7 → 59,7 |
|---|
| |
| static void fpu_context_fx_save(fpu_context_t *fctx) |
| { |
| __asm__ volatile ( |
| asm volatile ( |
| "fxsave %0" |
| : "=m"(*fctx) |
| ); |
| 67,7 → 67,7 |
|---|
| |
| static void fpu_context_fx_restore(fpu_context_t *fctx) |
| { |
| __asm__ volatile ( |
| asm volatile ( |
| "fxrstor %0" |
| : "=m"(*fctx) |
| ); |
| 103,7 → 103,7 |
|---|
| void fpu_init() |
| { |
| uint32_t help0 = 0, help1 = 0; |
| __asm__ volatile ( |
| asm volatile ( |
| "fninit;\n" |
| "stmxcsr %0\n" |
| "mov %0,%1;\n" |
| /trunk/kernel/arch/ia32/src/cpu/cpu.c |
|---|
| 71,7 → 71,7 |
|---|
| |
| void fpu_disable(void) |
| { |
| __asm__ volatile ( |
| asm volatile ( |
| "mov %%cr0,%%eax;" |
| "or $8,%%eax;" |
| "mov %%eax,%%cr0;" |
| 83,7 → 83,7 |
|---|
| |
| void fpu_enable(void) |
| { |
| __asm__ volatile ( |
| asm volatile ( |
| "mov %%cr0,%%eax;" |
| "and $0xffFFffF7,%%eax;" |
| "mov %%eax,%%cr0;" |
| /trunk/kernel/arch/ia32/src/pm.c |
|---|
| 147,7 → 147,7 |
|---|
| /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
| static void clean_IOPL_NT_flags(void) |
| { |
| __asm__ volatile ( |
| asm volatile ( |
| "pushfl\n" |
| "pop %%eax\n" |
| "and $0xffff8fff, %%eax\n" |
| 160,7 → 160,7 |
|---|
| /* Clean AM(18) flag in CR0 register */ |
| static void clean_AM_flag(void) |
| { |
| __asm__ volatile ( |
| asm volatile ( |
| "mov %%cr0, %%eax\n" |
| "and $0xfffbffff, %%eax\n" |
| "mov %%eax, %%cr0\n" |