/trunk/kernel/arch/amd64/src/fpu_context.c |
40,7 → 40,7 |
/** Save FPU (mmx, sse) context using fxsave instruction */ |
void fpu_context_save(fpu_context_t *fctx) |
{ |
__asm__ volatile ( |
asm volatile ( |
"fxsave %0" |
: "=m"(*fctx) |
); |
49,7 → 49,7 |
/** Restore FPU (mmx,sse) context using fxrstor instruction */ |
void fpu_context_restore(fpu_context_t *fctx) |
{ |
__asm__ volatile ( |
asm volatile ( |
"fxrstor %0" |
: "=m"(*fctx) |
); |
58,7 → 58,7 |
void fpu_init() |
{ |
/* TODO: Zero all SSE, MMX etc. registers */ |
__asm__ volatile ( |
asm volatile ( |
"fninit;" |
); |
} |
/trunk/kernel/arch/amd64/src/cpu/cpu.c |
76,7 → 76,7 |
*/ |
void cpu_setup_fpu(void) |
{ |
__asm__ volatile ( |
asm volatile ( |
"movq %%cr0, %%rax;" |
"btsq $1, %%rax;" /* cr0.mp */ |
"btrq $2, %%rax;" /* cr0.em */ |
99,7 → 99,7 |
*/ |
void fpu_disable(void) |
{ |
__asm__ volatile ( |
asm volatile ( |
"mov %%cr0,%%rax;" |
"bts $3,%%rax;" |
"mov %%rax,%%cr0;" |
111,7 → 111,7 |
|
void fpu_enable(void) |
{ |
__asm__ volatile ( |
asm volatile ( |
"mov %%cr0,%%rax;" |
"btr $3,%%rax;" |
"mov %%rax,%%cr0;" |