/trunk/kernel/genarch/include/kbd/z8530.h |
---|
42,7 → 42,7 |
extern bool z8530_belongs_to_kernel; |
extern void z8530_init(void); |
extern void z8530_init(devno_t devno, inr_t inr, uintptr_t vaddr); |
extern void z8530_poll(void); |
extern void z8530_grab(void); |
extern void z8530_release(void); |
/trunk/kernel/genarch/include/kbd/ns16550.h |
---|
40,7 → 40,7 |
#include <typedefs.h> |
#include <ddi/irq.h> |
extern void ns16550_init(void); |
extern void ns16550_init(devno_t devno, inr_t inr, uintptr_t vaddr); |
extern void ns16550_poll(void); |
extern void ns16550_grab(void); |
extern void ns16550_release(void); |
/trunk/kernel/genarch/src/kbd/ns16550.c |
---|
1,5 → 1,5 |
/* |
* Copyright (C) 2001-2004 Jakub Jermar |
* Copyright (C) 2001-2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
52,6 → 52,12 |
#define LSR_DATA_READY 0x01 |
/** Structure representing the ns16550. */ |
static ns16550_t ns16550; |
/** Structure for ns16550's IRQ. */ |
static irq_t ns16550_irq; |
/* |
* These codes read from ns16550 data register are silently ignored. |
*/ |
81,21 → 87,37 |
/* TODO */ |
} |
/** Initialize ns16550. */ |
void ns16550_init(void) |
/** Initialize ns16550. |
* |
* @param devno Device number. |
* @param inr Interrupt number. |
* @param vaddr Virtual address of device's registers. |
*/ |
void ns16550_init(devno_t devno, inr_t inr, uintptr_t vaddr) |
{ |
ns16550_grab(); |
chardev_initialize("ns16550_kbd", &kbrd, &ops); |
stdin = &kbrd; |
ns16550.devno = devno; |
ns16550.reg = (uint8_t *) vaddr; |
irq_initialize(&ns16550_irq); |
ns16550_irq.devno = devno; |
ns16550_irq.inr = inr; |
ns16550_irq.claim = ns16550_claim; |
ns16550_irq.handler = ns16550_irq_handler; |
irq_register(&ns16550_irq); |
sysinfo_set_item_val("kbd", NULL, true); |
sysinfo_set_item_val("kbd.irq", NULL, 0); |
sysinfo_set_item_val("kbd.address.virtual", NULL, (uintptr_t) kbd_virt_address); |
sysinfo_set_item_val("kbd.devno", NULL, devno); |
sysinfo_set_item_val("kbd.inr", NULL, inr); |
sysinfo_set_item_val("kbd.address.virtual", NULL, vaddr); |
ns16550_ier_write(IER_ERBFI); /* enable receiver interrupt */ |
ns16550_ier_write(&ns16550, IER_ERBFI); /* enable receiver interrupt */ |
while (ns16550_lsr_read() & LSR_DATA_READY) |
(void) ns16550_rbr_read(); |
while (ns16550_lsr_read(&ns16550) & LSR_DATA_READY) |
(void) ns16550_rbr_read(&ns16550); |
} |
/** Process ns16550 interrupt. |
129,9 → 151,9 |
while(!(ch = active_read_buff_read())) { |
uint8_t x; |
while (!(ns16550_lsr_read() & LSR_DATA_READY)) |
while (!(ns16550_lsr_read(&ns16550) & LSR_DATA_READY)) |
; |
x = ns16550_rbr_read(); |
x = ns16550_rbr_read(&ns16550); |
if (x != IGNORE_CODE) { |
if (x & KEY_RELEASE) |
key_released(x ^ KEY_RELEASE); |
150,8 → 172,8 |
{ |
uint8_t x; |
while (ns16550_lsr_read() & LSR_DATA_READY) { |
x = ns16550_rbr_read(); |
while (ns16550_lsr_read(&ns16550) & LSR_DATA_READY) { |
x = ns16550_rbr_read(&ns16550); |
if (x != IGNORE_CODE) { |
if (x & KEY_RELEASE) |
key_released(x ^ KEY_RELEASE); |
/trunk/kernel/genarch/src/kbd/z8530.c |
---|
60,6 → 60,9 |
bool z8530_belongs_to_kernel = true; |
static z8530_t z8530; /**< z8530 device structure. */ |
static irq_t z8530_irq; /**< z8530's IRQ. */ |
static void z8530_suspend(chardev_t *); |
static void z8530_resume(chardev_t *); |
84,29 → 87,40 |
} |
/** Initialize z8530. */ |
void z8530_init(void) |
void z8530_init(devno_t devno, inr_t inr, uintptr_t vaddr) |
{ |
chardev_initialize("z8530_kbd", &kbrd, &ops); |
stdin = &kbrd; |
z8530.devno = devno; |
z8530.reg = (uint8_t *) vaddr; |
irq_initialize(&z8530_irq); |
z8530_irq.devno = devno; |
z8530_irq.inr = inr; |
z8530_irq.claim = z8530_claim; |
z8530_irq.handler = z8530_irq_handler; |
irq_register(&z8530_irq); |
sysinfo_set_item_val("kbd", NULL, true); |
sysinfo_set_item_val("kbd.irq", NULL, 0); |
sysinfo_set_item_val("kbd.address.virtual", NULL, (uintptr_t) kbd_virt_address); |
sysinfo_set_item_val("kbd.devno", NULL, devno); |
sysinfo_set_item_val("kbd.inr", NULL, inr); |
sysinfo_set_item_val("kbd.address.virtual", NULL, vaddr); |
(void) z8530_read_a(RR8); |
(void) z8530_read_a(&z8530, RR8); |
/* |
* Clear any pending TX interrupts or we never manage |
* to set FHC UART interrupt state to idle. |
*/ |
z8530_write_a(WR0, WR0_TX_IP_RST); |
z8530_write_a(&z8530, WR0, WR0_TX_IP_RST); |
z8530_write_a(WR1, WR1_IARCSC); /* interrupt on all characters */ |
z8530_write_a(&z8530, WR1, WR1_IARCSC); /* interrupt on all characters */ |
/* 8 bits per character and enable receiver */ |
z8530_write_a(WR3, WR3_RX8BITSCH | WR3_RX_ENABLE); |
z8530_write_a(&z8530, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE); |
z8530_write_a(WR9, WR9_MIE); /* Master Interrupt Enable. */ |
z8530_write_a(&z8530, WR9, WR9_MIE); /* Master Interrupt Enable. */ |
} |
/** Process z8530 interrupt. |
139,9 → 153,9 |
while(!(ch = active_read_buff_read())) { |
uint8_t x; |
while (!(z8530_read_a(RR0) & RR0_RCA)) |
while (!(z8530_read_a(&z8530, RR0) & RR0_RCA)) |
; |
x = z8530_read_a(RR8); |
x = z8530_read_a(&z8530, RR8); |
if (x != IGNORE_CODE) { |
if (x & KEY_RELEASE) |
key_released(x ^ KEY_RELEASE); |
160,8 → 174,8 |
{ |
uint8_t x; |
while (z8530_read_a(RR0) & RR0_RCA) { |
x = z8530_read_a(RR8); |
while (z8530_read_a(&z8530, RR0) & RR0_RCA) { |
x = z8530_read_a(&z8530, RR8); |
if (x != IGNORE_CODE) { |
if (x & KEY_RELEASE) |
key_released(x ^ KEY_RELEASE); |
173,7 → 187,7 |
irq_ownership_t z8530_claim(void) |
{ |
return (z8530_read_a(RR0) & RR0_RCA); |
return (z8530_read_a(&z8530, RR0) & RR0_RCA); |
} |
void z8530_irq_handler(irq_t *irq, void *arg, ...) |
/trunk/kernel/generic/include/ddi/irq.h |
---|
37,6 → 37,10 |
#include <arch/types.h> |
#include <adt/list.h> |
#include <ipc/ipc.h> |
#include <ipc/irq.h> |
#include <atomic.h> |
#include <synch/spinlock.h> |
typedef enum { |
IRQ_DECLINE, /**< Decline to service. */ |
62,13 → 66,18 |
/** Hash table link. */ |
link_t link; |
/** Lock protecting everything in this structure |
* except the link member. When both the IRQ |
* hash table lock and this lock are to be acquired, |
* this lock must not be taken first. |
*/ |
SPINLOCK_DECLARE(lock); |
/** Unique device number. -1 if not yet assigned. */ |
devno_t devno; |
/** Actual IRQ number. -1 if not yet assigned. */ |
inr_t inr; |
/** Task ID of the task to be notified about the IRQ or 0. */ |
task_id_t notif; |
/** Trigger level of the IRQ.*/ |
irq_trigger_t trigger; |
/** Claim ownership of the IRQ. */ |
77,6 → 86,14 |
irq_handler_t handler; |
/** Argument for the handler. */ |
void *arg; |
/** Answerbox of the task that wanted to be notified. */ |
answerbox_t *notif_answerbox; |
/** Pseudo-code to be performed by the top-half |
* before a notification is sent. */ |
irq_code_t *code; |
/** Counter of IRQ notifications. */ |
atomic_t counter; |
}; |
extern void irq_init(count_t inrs, count_t chains); |
/trunk/kernel/generic/src/ddi/irq.c |
---|
63,6 → 63,7 |
#include <arch/types.h> |
#include <typedefs.h> |
#include <synch/spinlock.h> |
#include <atomic.h> |
#include <arch.h> |
/** |
127,13 → 128,16 |
void irq_initialize(irq_t *irq) |
{ |
link_initialize(&irq->link); |
spinlock_initialize(&irq->lock, "irq.lock"); |
irq->inr = -1; |
irq->devno = -1; |
irq->notif = 0; |
irq->trigger = 0; |
irq->claim = NULL; |
irq->handler = NULL; |
irq->arg = NULL; |
irq->notif_answerbox = NULL; |
irq->code = NULL; |
atomic_set(&irq->counter, 0); |
} |
/** Register IRQ for device. |
220,8 → 224,13 |
{ |
irq_t *irq = hash_table_get_instance(item, irq_t, link); |
inr_t *inr = (inr_t *) key; |
bool rv; |
return ((irq->inr == *inr) && (irq->claim() == IRQ_ACCEPT)); |
spinlock_lock(&irq->lock); |
rv = ((irq->inr == *inr) && (irq->claim() == IRQ_ACCEPT)); |
spinlock_unlock(&irq->lock); |
return rv; |
} |
/** Compute hash index for the key. |
259,8 → 268,13 |
bool irq_lin_compare(unative_t *key, count_t keys, link_t *item) |
{ |
irq_t *irq = list_get_instance(item, irq_t, link); |
bool rv; |
return (irq->claim() == IRQ_ACCEPT); |
spinlock_lock(&irq->lock); |
rv = (irq->claim() == IRQ_ACCEPT); |
spinlock_unlock(&irq->lock); |
return rv; |
} |
/** @} |
/trunk/kernel/arch/sparc64/include/drivers/z8530.h |
---|
91,42 → 91,48 |
/* Read Register 0 */ |
#define RR0_RCA (0x1<<0) /** Receive Character Available. */ |
static inline void z8530_write(index_t chan, uint8_t reg, uint8_t val) |
/** Structure representing the z8530 device. */ |
typedef struct { |
devno_t devno; |
volatile uint8_t *reg; /** Memory mapped registers of the z8530. */ |
} z8530_t; |
static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val) |
{ |
/* |
* Registers 8-15 will automatically issue the Point High |
* command as their bit 3 is 1. |
*/ |
kbd_virt_address[WR0+chan] = reg; /* select register */ |
kbd_virt_address[WR0+chan] = val; /* write value */ |
dev->reg[WR0+chan] = reg; /* select register */ |
dev->reg[WR0+chan] = val; /* write value */ |
} |
static inline void z8530_write_a(uint8_t reg, uint8_t val) |
static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val) |
{ |
z8530_write(Z8530_CHAN_A, reg, val); |
z8530_write(dev, Z8530_CHAN_A, reg, val); |
} |
static inline void z8530_write_b(uint8_t reg, uint8_t val) |
static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val) |
{ |
z8530_write(Z8530_CHAN_B, reg, val); |
z8530_write(dev, Z8530_CHAN_B, reg, val); |
} |
static inline uint8_t z8530_read(index_t chan, uint8_t reg) |
static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg) |
{ |
/* |
* Registers 8-15 will automatically issue the Point High |
* command as their bit 3 is 1. |
*/ |
kbd_virt_address[WR0+chan] = reg; /* select register */ |
return kbd_virt_address[WR0+chan]; |
dev->reg[WR0+chan] = reg; /* select register */ |
return dev->reg[WR0+chan]; |
} |
static inline uint8_t z8530_read_a(uint8_t reg) |
static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg) |
{ |
return z8530_read(Z8530_CHAN_A, reg); |
return z8530_read(dev, Z8530_CHAN_A, reg); |
} |
static inline uint8_t z8530_read_b(uint8_t reg) |
static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg) |
{ |
return z8530_read(Z8530_CHAN_B, reg); |
return z8530_read(dev, Z8530_CHAN_B, reg); |
} |
#endif |
/trunk/kernel/arch/sparc64/include/drivers/kbd.h |
---|
46,8 → 46,6 |
extern kbd_type_t kbd_type; |
extern volatile uint8_t *kbd_virt_address; |
extern void kbd_init(ofw_tree_node_t *node); |
#endif |
/trunk/kernel/arch/sparc64/include/drivers/ns16550.h |
---|
50,44 → 50,50 |
#define LCR_DLAB 0x80 /** Divisor Latch Access bit. */ |
static inline uint8_t ns16550_rbr_read(void) |
/** Structure representing the ns16550 device. */ |
typedef struct { |
devno_t devno; |
volatile uint8_t *reg; /** Memory mapped registers of the ns16550. */ |
} ns16550_t; |
static inline uint8_t ns16550_rbr_read(ns16550_t *dev) |
{ |
return kbd_virt_address[RBR_REG]; |
return dev->reg[RBR_REG]; |
} |
static inline uint8_t ns16550_ier_read(void) |
static inline uint8_t ns16550_ier_read(ns16550_t *dev) |
{ |
return kbd_virt_address[IER_REG]; |
return dev->reg[IER_REG]; |
} |
static inline void ns16550_ier_write(uint8_t v) |
static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v) |
{ |
kbd_virt_address[IER_REG] = v; |
dev->reg[IER_REG] = v; |
} |
static inline uint8_t ns16550_iir_read(void) |
static inline uint8_t ns16550_iir_read(ns16550_t *dev) |
{ |
return kbd_virt_address[IIR_REG]; |
return dev->reg[IIR_REG]; |
} |
static inline void ns16550_fcr_write(uint8_t v) |
static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v) |
{ |
kbd_virt_address[FCR_REG] = v; |
dev->reg[FCR_REG] = v; |
} |
static inline uint8_t ns16550_lcr_read(void) |
static inline uint8_t ns16550_lcr_read(ns16550_t *dev) |
{ |
return kbd_virt_address[LCR_REG]; |
return dev->reg[LCR_REG]; |
} |
static inline void ns16550_lcr_write(uint8_t v) |
static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v) |
{ |
kbd_virt_address[LCR_REG] = v; |
dev->reg[LCR_REG] = v; |
} |
static inline uint8_t ns16550_lsr_read(void) |
static inline uint8_t ns16550_lsr_read(ns16550_t *dev) |
{ |
return kbd_virt_address[LSR_REG]; |
return dev->reg[LSR_REG]; |
} |
#endif |
/trunk/kernel/arch/sparc64/src/drivers/kbd.c |
---|
49,12 → 49,8 |
#include <func.h> |
#include <print.h> |
volatile uint8_t *kbd_virt_address = NULL; |
kbd_type_t kbd_type = KBD_UNKNOWN; |
static irq_t kbd_irq; |
/** Initialize keyboard. |
* |
* Traverse OpenFirmware device tree in order to find necessary |
102,10 → 98,9 |
uintptr_t pa; |
size_t size; |
int inr; |
inr_t inr; |
devno_t devno = device_assign_devno(); |
irq_initialize(&kbd_irq); |
switch (kbd_type) { |
case KBD_Z8530: |
size = ((ofw_fhc_reg_t *) prop->value)->size; |
116,13 → 111,6 |
if (!ofw_fhc_map_interrupt(node->parent, ((ofw_fhc_reg_t *) prop->value), interrupts, &inr)) { |
printf("Failed to determine keyboard interrupt.\n"); |
return; |
} else { |
kbd_irq.inr = inr; |
kbd_irq.devno = device_assign_devno(); |
kbd_irq.trigger = IRQ_TRIGGER_LEVEL; |
kbd_irq.claim = z8530_claim; |
kbd_irq.handler = z8530_irq_handler; |
irq_register(&kbd_irq); |
} |
break; |
135,14 → 123,7 |
if (!ofw_ebus_map_interrupt(node->parent, ((ofw_ebus_reg_t *) prop->value), interrupts, &inr)) { |
printf("Failed to determine keyboard interrupt.\n"); |
return; |
} else { |
kbd_irq.inr = inr; |
kbd_irq.devno = device_assign_devno(); |
kbd_irq.trigger = IRQ_TRIGGER_LEVEL; |
kbd_irq.claim = ns16550_claim; |
kbd_irq.handler = ns16550_irq_handler; |
irq_register(&kbd_irq); |
} |
}; |
break; |
default: |
157,17 → 138,17 |
*/ |
aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE); |
offset = pa - aligned_addr; |
kbd_virt_address = (uint8_t *) hw_map(aligned_addr, offset + size) + offset; |
uintptr_t vaddr = hw_map(aligned_addr, offset + size) + offset; |
switch (kbd_type) { |
#ifdef CONFIG_Z8530 |
case KBD_Z8530: |
z8530_init(); |
z8530_init(devno, inr, vaddr); |
break; |
#endif |
#ifdef CONFIG_NS16550 |
case KBD_NS16550: |
ns16550_init(); |
ns16550_init(devno, inr, vaddr); |
break; |
#endif |
default: |