/trunk/kernel/arch/arm32/src/exception.c |
---|
214,7 → 214,8 |
/* relative address (related to exc. vector) of the word |
* where handler's address is stored |
*/ |
volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
PREFETCH_OFFSET; |
/* make it LDR instruction and store at exception vector */ |
*vector = handler_address_ptr | LDR_OPCODE; |
286,13 → 287,8 |
*/ |
static void swi_exception(int exc_no, istate_t *istate) |
{ |
/* |
dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, |
istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
*/ |
istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
istate->r3, istate->r4); |
istate->r3, istate->r4, istate->r5, istate->r6); |
} |
/** Interrupt Exception handler. |
/trunk/uspace/lib/libc/arch/arm32/src/syscall.c |
---|
50,21 → 50,25 |
* @return Syscall return value. |
*/ |
sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, const sysarg_t p3, |
const sysarg_t p4, const syscall_t id) |
const sysarg_t p4, const sysarg_t p5, const sysarg_t p6, const syscall_t id) |
{ |
register sysarg_t __arm_reg_r0 asm("r0") = p1; |
register sysarg_t __arm_reg_r1 asm("r1") = p2; |
register sysarg_t __arm_reg_r2 asm("r2") = p3; |
register sysarg_t __arm_reg_r3 asm("r3") = p4; |
register sysarg_t __arm_reg_r4 asm("r4") = id; |
register sysarg_t __arm_reg_r4 asm("r4") = p5; |
register sysarg_t __arm_reg_r5 asm("r5") = p6; |
register sysarg_t __arm_reg_r6 asm("r6") = id; |
asm volatile ( "swi" |
: "=r" (__arm_reg_r0) |
: "r" (__arm_reg_r0), |
"r" (__arm_reg_r1), |
"r" (__arm_reg_r2), |
"r" (__arm_reg_r3), |
"r" (__arm_reg_r4) |
: "r" (__arm_reg_r0), |
"r" (__arm_reg_r1), |
"r" (__arm_reg_r2), |
"r" (__arm_reg_r3), |
"r" (__arm_reg_r4), |
"r" (__arm_reg_r5), |
"r" (__arm_reg_r6) |
); |
return __arm_reg_r0; |