/trunk/boot/arch/arm32/loader/main.h |
---|
68,6 → 68,7 |
} bootinfo_t; |
extern void bootstrap(void); |
#endif |
/trunk/boot/arch/arm32/loader/asm.h |
---|
62,11 → 62,12 |
* @param bootinfo Structure holding information about loaded tasks. |
* @param bootinfo_size Size of the bootinfo structure. |
*/ |
extern void jump_to_kernel(void *entry, void *bootinfo, |
unsigned int bootinfo_size) __attribute__((noreturn)); |
extern void jump_to_kernel(void *entry, void *bootinfo, unsigned int bootinfo_size) __attribute__((noreturn)); |
#endif |
/** @} |
*/ |
/trunk/boot/arch/arm32/loader/mm.c |
---|
1,95 → 1,94 |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32boot |
* @{ |
*/ |
/** @file |
* @brief Memory management used while booting the kernel. |
*/ |
#include "mm.h" |
/** Initializes "section" page table entry. |
* |
* Will be readable/writable by kernel with no access from user mode. |
* Will belong to domain 0. No cache or buffering is enabled. |
* |
* @param pte Section entry to initialize. |
* @param frame First frame in the section (frame number). |
* |
* @note If frame is not 1MB aligned, first lower 1MB aligned frame will be |
* used. |
*/ |
static void init_pte_level0_section(pte_level0_section_t* pte, |
unsigned int frame) |
{ |
pte->descriptor_type = PTE_DESCRIPTOR_SECTION; |
pte->bufferable = 0; |
pte->cacheable = 0; |
pte->impl_specific = 0; |
pte->domain = 0; |
pte->should_be_zero_1 = 0; |
pte->access_permission = PTE_AP_USER_NO_KERNEL_RW; |
pte->should_be_zero_2 = 0; |
pte->section_base_addr = frame; |
} |
/** Initializes page table used while booting the kernel. */ |
static void init_page_table(void) |
{ |
int i; |
const unsigned int first_kernel_page = ADDR2PFN(PA2KA(0)); |
/* Create 1:1 virtual-physical mapping (in lower 2GB). */ |
for (i = 0; i < first_kernel_page; i++) { |
init_pte_level0_section(&page_table[i], i); |
} |
/* |
* Create 1:1 virtual-physical mapping in kernel space (upper 2GB), |
* physical addresses start from 0. |
*/ |
for (i = first_kernel_page; i < PTL0_ENTRIES; i++) { |
init_pte_level0_section(&page_table[i], i - first_kernel_page); |
} |
} |
/** Starts the MMU - initializes page table and enables paging. */ |
void mmu_start() { |
init_page_table(); |
set_ptl0_address(page_table); |
enable_paging(); |
} |
/** @} |
*/ |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32boot |
* @{ |
*/ |
/** @file |
* @brief Memory management used while booting the kernel. |
*/ |
#include "mm.h" |
/** Initializes "section" page table entry. |
* |
* Will be readable/writable by kernel with no access from user mode. |
* Will belong to domain 0. No cache or buffering is enabled. |
* |
* @param pte Section entry to initialize. |
* @param frame First frame in the section (frame number). |
* |
* @note If frame is not 1MB aligned, first lower 1MB aligned frame will be used. |
*/ |
static void init_pte_level0_section(pte_level0_section_t* pte, unsigned int frame) |
{ |
pte->descriptor_type = PTE_DESCRIPTOR_SECTION; |
pte->bufferable = 0; |
pte->cacheable = 0; |
pte->impl_specific = 0; |
pte->domain = 0; |
pte->should_be_zero_1 = 0; |
pte->access_permission = PTE_AP_USER_NO_KERNEL_RW; |
pte->should_be_zero_2 = 0; |
pte->section_base_addr = frame; |
} |
/** Initializes page table used while booting the kernel. */ |
static void init_page_table(void) |
{ |
int i; |
const unsigned int first_kernel_page = ADDR2PFN(PA2KA(0)); |
// create 1:1 virtual-physical mapping (in lower 2GB) |
for (i = 0; i < first_kernel_page; i++) { |
init_pte_level0_section(&page_table[i], i); |
} |
// create 1:1 virtual-physical mapping in kernel space (upper 2GB), |
// physical addresses start from 0 |
for (i = first_kernel_page; i < PTL0_ENTRIES; i++) { |
init_pte_level0_section(&page_table[i], i - first_kernel_page); |
} |
} |
/** Starts the MMU - initializes page table and enables paging. */ |
void mmu_start() { |
init_page_table(); |
set_ptl0_address(page_table); |
enable_paging(); |
} |
/** @} |
*/ |
/trunk/boot/arch/arm32/loader/print/gxemul.c |
---|
48,7 → 48,7 |
*/ |
static void putc(char ch) |
{ |
*((volatile char *) PUTC_ADDRESS) = ch; |
*((volatile char *)PUTC_ADDRESS) = ch; |
} |
/trunk/boot/arch/arm32/loader/mm.h |
---|
1,166 → 1,160 |
/* |
* Copyright (c) 2007 Pavel Jancik |
* Copyright (c) 2007 Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32boot |
* @{ |
*/ |
/** @file |
* @brief Memory management used while booting the kernel. |
* |
* So called "section" paging is used while booting the kernel. The term |
* "section" comes from the ARM architecture specification and stands for the |
* following: one-level paging, 1MB sized pages, 4096 entries in the page |
* table. |
*/ |
#ifndef BOOT_arm32__MM_H |
#define BOOT_arm32__MM_H |
#ifndef __ASM__ |
#include "types.h" |
#endif |
/** Frame width. */ |
#define FRAME_WIDTH 20 |
/** Frame size. */ |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
/** Page size in 2-level paging which is switched on later after the kernel |
* initialization. |
*/ |
#define KERNEL_PAGE_SIZE (1 << 12) |
#ifndef __ASM__ |
/** Converts kernel address to physical address. */ |
# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
/** Converts physical address to kernel address. */ |
# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
#else |
# define KA2PA(x) ((x) - 0x80000000) |
# define PA2KA(x) ((x) + 0x80000000) |
#endif |
/** Number of entries in PTL0. */ |
#define PTL0_ENTRIES (1 << 12) /* 4096 */ |
/** Size of an entry in PTL0. */ |
#define PTL0_ENTRY_SIZE 4 |
/** Returns number of frame the address belongs to. */ |
#define ADDR2PFN(addr) (((uintptr_t) (addr)) >> FRAME_WIDTH) |
/** Describes "section" page table entry (one-level paging with 1MB sized pages). */ |
#define PTE_DESCRIPTOR_SECTION 0x2 |
/** Page table access rights: user - no access, kernel - read/write. */ |
#define PTE_AP_USER_NO_KERNEL_RW 0x1 |
#ifndef __ASM__ |
/** Page table level 0 entry - "section" format is used (one-level paging, 1MB |
* sized pages). Used only while booting the kernel. |
*/ |
typedef struct { |
unsigned descriptor_type : 2; |
unsigned bufferable : 1; |
unsigned cacheable : 1; |
unsigned impl_specific : 1; |
unsigned domain : 4; |
unsigned should_be_zero_1 : 1; |
unsigned access_permission : 2; |
unsigned should_be_zero_2 : 8; |
unsigned section_base_addr : 12; |
} __attribute__ ((packed)) pte_level0_section_t; |
/** Page table that holds 1:1 virtual to physical mapping used while booting the |
* kernel. |
*/ |
extern pte_level0_section_t page_table[PTL0_ENTRIES]; |
extern void mmu_start(void); |
/** Enables paging. */ |
static inline void enable_paging() |
{ |
/* c3 - each two bits controls access to the one of domains (16) |
* 0b01 - behave as a client (user) of a domain |
*/ |
asm volatile ( |
/* behave as a client of domains */ |
"ldr r0, =0x55555555\n" |
"mcr p15, 0, r0, c3, c0, 0\n" |
/* current settings */ |
"mrc p15, 0, r0, c1, c0, 0\n" |
/* mask to enable paging */ |
"ldr r1, =0x00000001\n" |
"orr r0, r0, r1\n" |
/* store settings */ |
"mcr p15, 0, r0, c1, c0, 0\n" |
: |
: |
: "r0", "r1" |
); |
} |
/** Sets the address of level 0 page table to CP15 register 2. |
* |
* @param pt Address of a page table to set. |
*/ |
static inline void set_ptl0_address(pte_level0_section_t* pt) |
{ |
asm volatile ( |
"mcr p15, 0, %0, c2, c0, 0\n" |
: |
: "r" (pt) |
); |
} |
#endif |
#endif |
/** @} |
*/ |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32boot |
* @{ |
*/ |
/** @file |
* @brief Memory management used while booting the kernel. |
* |
* So called "section" paging is used while booting the kernel. The term "section" |
* comes from the ARM architecture specification and stands for the following: |
* one-level paging, 1MB sized pages, 4096 entries in the page table. |
*/ |
#ifndef BOOT_arm32__MM_H |
#define BOOT_arm32__MM_H |
#ifndef __ASM__ |
#include "types.h" |
#endif |
/** Frame width. */ |
#define FRAME_WIDTH 20 |
/** Frame size. */ |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
/** Page size in 2-level paging which is switched on later after the kernel initialization. */ |
#define KERNEL_PAGE_SIZE (1 << 12) |
#ifndef __ASM__ |
/** Converts kernel address to physical address. */ |
# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
/** Converts physical address to kernel address. */ |
# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
#else |
# define KA2PA(x) ((x) - 0x80000000) |
# define PA2KA(x) ((x) + 0x80000000) |
#endif |
/** Number of entries in PTL0. */ |
#define PTL0_ENTRIES (1<<12) /* 4096 */ |
/** Size of an entry in PTL0. */ |
#define PTL0_ENTRY_SIZE 4 |
/** Returns number of frame the address belongs to. */ |
#define ADDR2PFN( addr ) ( ((uintptr_t)(addr)) >> FRAME_WIDTH ) |
/** Describes "section" page table entry (one-level paging with 1MB sized pages). */ |
#define PTE_DESCRIPTOR_SECTION 0x2 |
/** Page table access rights: user - no access, kernel - read/write. */ |
#define PTE_AP_USER_NO_KERNEL_RW 0x1 |
#ifndef __ASM__ |
/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized |
* pages). Used only while booting the kernel. |
*/ |
typedef struct { |
unsigned descriptor_type : 2; |
unsigned bufferable : 1; |
unsigned cacheable : 1; |
unsigned impl_specific : 1; |
unsigned domain : 4; |
unsigned should_be_zero_1 : 1; |
unsigned access_permission : 2; |
unsigned should_be_zero_2 : 8; |
unsigned section_base_addr : 12; |
} __attribute__ ((packed)) pte_level0_section_t; |
/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */ |
extern pte_level0_section_t page_table[PTL0_ENTRIES]; |
extern void mmu_start(void); |
/** Enables paging. */ |
static inline void enable_paging() |
{ |
/* c3 - each two bits controls access to the one of domains (16) |
* 0b01 - behave as a client (user) of a domain |
*/ |
asm volatile ( |
// behave as a client of domains |
"ldr r0, =0x55555555 \n" |
"mcr p15, 0, r0, c3, c0, 0 \n" |
// current settings |
"mrc p15, 0, r0, c1, c0, 0 \n" |
// mask to enable paging |
"ldr r1, =0x00000001 \n" |
"orr r0, r0, r1 \n" |
// store settings |
"mcr p15, 0, r0, c1, c0, 0 \n" |
: |
: |
: "r0", "r1" |
); |
} |
/** Sets the address of level 0 page table to CP15 register 2. |
* |
* @param pt Address of a page table to set. |
*/ |
static inline void set_ptl0_address(pte_level0_section_t* pt) |
{ |
asm volatile ( |
"mcr p15, 0, %0, c2, c0, 0 \n" |
: |
: "r"(pt) |
); |
} |
#endif |
#endif |
/** @} |
*/ |
/trunk/boot/arch/arm32/loader/types.h |
---|
57,3 → 57,4 |
/** @} |
*/ |
/trunk/boot/arch/mips32/loader/regname.h |
---|
26,8 → 26,8 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef BOOT_mips32_REGNAME_H_ |
#define BOOT_mips32_REGNAME_H_ |
#ifndef __mips32_REGNAME_H_ |
#define __mips32_REGNAME_H_ |
#define zero 0 |
#define at 1 |
85,4 → 85,5 |
#define depc 24 |
#define eepc 30 |
#endif /* _REGNAME_H_ */ |
/trunk/boot/arch/mips32/loader/asm.h |
---|
26,13 → 26,13 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef BOOT_mips32_ASM_H_ |
#define BOOT_mips32_ASM_H_ |
#ifndef __ASM_H__ |
#define __ASM_H__ |
#define PAGE_SIZE 16384 |
#define PAGE_WIDTH 14 |
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
void jump_to_kernel(void *entry, void *bootinfo, unsigned int bootinfo_size) __attribute__((noreturn)); |
/trunk/boot/arch/mips32/loader/main.h |
---|
26,8 → 26,8 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef BOOT_mips32_MAIN_H_ |
#define BOOT_mips32_MAIN_H_ |
#ifndef __MAIN_H__ |
#define __MAIN_H__ |
/** Align to the nearest higher address. |
* |
/trunk/boot/arch/mips32/loader/types.h |
---|
26,8 → 26,8 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef BOOT_mips32_TYPES_H_ |
#define BOOT_mips32_TYPES_H_ |
#ifndef TYPES_H__ |
#define TYPES_H__ |
#include <gentypes.h> |
/trunk/boot/arch/mips32/loader/msim.h |
---|
26,8 → 26,8 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef BOOT_mips32_MSIM_H_ |
#define BOOT_mips32_MSIM_H_ |
#ifndef __MSIM_H__ |
#define __MSIM_H__ |
extern void init(void); |
extern void halt(void); |
/trunk/uspace/libc/arch/arm32/include/atomic.h |
---|
49,13 → 49,13 |
volatile long * mem = &(val->count); |
asm volatile ( |
"1:\n" |
"ldr r2, [%1]\n" |
"add r3, r2, %2\n" |
"str r3, %0\n" |
"swp r3, r3, [%1]\n" |
"cmp r3, r2\n" |
"bne 1b\n" |
"1: \n" |
"ldr r2, [%1] \n" |
"add r3, r2, %2 \n" |
"str r3, %0 \n" |
"swp r3, r3, [%1] \n" |
"cmp r3, r2 \n" |
"bne 1b \n" |
: "=m" (ret) |
: "r" (mem), "r" (i) |
70,10 → 70,7 |
* |
* @param val Variable to be incremented. |
*/ |
static inline void atomic_inc(atomic_t *val) |
{ |
atomic_add(val, 1); |
} |
static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); } |
/** Atomic decrement. |
80,10 → 77,7 |
* |
* @param val Variable to be decremented. |
*/ |
static inline void atomic_dec(atomic_t *val) |
{ |
atomic_add(val, -1); |
} |
static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); } |
/** Atomic pre-increment. |
91,10 → 85,7 |
* @param val Variable to be incremented. |
* @return Value after incrementation. |
*/ |
static inline long atomic_preinc(atomic_t *val) |
{ |
return atomic_add(val, 1); |
} |
static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1); } |
/** Atomic pre-decrement. |
102,10 → 93,7 |
* @param val Variable to be decremented. |
* @return Value after decrementation. |
*/ |
static inline long atomic_predec(atomic_t *val) |
{ |
return atomic_add(val, -1); |
} |
static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1); } |
/** Atomic post-increment. |
113,10 → 101,7 |
* @param val Variable to be incremented. |
* @return Value before incrementation. |
*/ |
static inline long atomic_postinc(atomic_t *val) |
{ |
return atomic_add(val, 1) - 1; |
} |
static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1) - 1; } |
/** Atomic post-decrement. |
124,10 → 109,7 |
* @param val Variable to be decremented. |
* @return Value before decrementation. |
*/ |
static inline long atomic_postdec(atomic_t *val) |
{ |
return atomic_add(val, -1) + 1; |
} |
static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1) + 1; } |
#endif |
/trunk/uspace/libc/arch/arm32/include/thread.h |
---|
60,7 → 60,7 |
*/ |
static inline void __tcb_set(tcb_t *tcb) |
{ |
void *tls = (void *) tcb; |
void *tls = (void *)tcb; |
tls += sizeof(tcb_t) + ARM_TP_OFFSET; |
asm volatile ( |
"mov r9, %0" |
81,7 → 81,7 |
"mov %0, r9" |
: "=r"(ret) |
); |
return (tcb_t *) (ret - ARM_TP_OFFSET - sizeof(tcb_t)); |
return (tcb_t *)(ret - ARM_TP_OFFSET - sizeof(tcb_t)); |
} |