WebSVN – HelenOS – Path Comparison – / – /tags/0.1.0/SPARTAN/arch/ia64/ Rev 1967 and /tags/0.1.0/SPARTAN/arch/ia64/ Rev 1968

Ignore whitespace Rev 1967 → Rev 1968

 /tags/0.1.0/SPARTAN/arch/ia64/include/context.h
 ,0 → 1,103
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_CONTEXT_H__
+#define __ia64_CONTEXT_H__
+#include <arch/types.h>
+#include <typedefs.h>
+#include <align.h>
+#include <arch/stack.h>
+/*
+ * context_save() and context_restore() are both leaf procedures.
+ * No need to allocate scratch area.
+ *
+ * One item is put onto the stack to support get_stack_base().
+ */
+#define SP_DELTA    (0+ALIGN(STACK_ITEM_SIZE, STACK_ALIGNMENT))
+#define PFM_MASK    (~0x3fffffffff)
+#ifdef context_set
+#undef context_set
+#endif
+#define context_set(c, _pc, stack, size)                                \
+    (c)->pc = (__address) _pc;                                  \
+    (c)->bsp = ((__address) stack) + ALIGN(sizeof(the_t), REGISTER_STACK_ALIGNMENT);        \
+    (c)->ar_pfs &= PFM_MASK;                                    \
+    (c)->sp = ((__address) stack) + ALIGN((size), STACK_ALIGNMENT) - SP_DELTA;
+/*
+ * Only save registers that must be preserved across
+ * function calls.
+ */
+struct context {
+    /*
+     * Application registers
+     */
+    __u64 ar_pfs;
+    __u64 ar_unat_caller;
+    __u64 ar_unat_callee;
+    __u64 ar_rsc;
+    __address bsp;      /* ar_bsp */
+    __u64 ar_rnat;
+    __u64 ar_lc;
+    /*
+     * General registers
+     */
+    __u64 r1;
+    __u64 r4;
+    __u64 r5;
+    __u64 r6;
+    __u64 r7;
+    __address sp;       /* r12 */
+    __u64 r13;
+    /*
+     * Branch registers
+     */
+    __address pc;       /* b0 */
+    __u64 b1;
+    __u64 b2;
+    __u64 b3;
+    __u64 b4;
+    __u64 b5;
+    /*
+     * Predicate registers
+     */
+    __u64 pr;
+    ipl_t ipl;
+} __attribute__ ((packed));
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/drivers/it.h
 ,0 → 1,43
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_IT_H__
+#define __ia64_IT_H__
+/*
+ * Unfortunately, Ski does not emulate PAL,
+ * so we can't read the real frequency ratios
+ * from firmware.
+ *
+ */
+#define IT_DELTA        100000
+extern void it_init(void);
+extern void it_interrupt(void);
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/stack.h
 ,0 → 1,37
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_STACK_H__
+#define __ia64_STACK_H__
+#define STACK_ITEM_SIZE         8
+#define STACK_ALIGNMENT         16
+#define STACK_SCRATCH_AREA_SIZE     16
+#define REGISTER_STACK_ALIGNMENT    8
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/interrupt.h
 ,0 → 1,39
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_INTERRUPT_H__
+#define __ia64_INTERRUPT_H__
+#define INTERRUPT_TIMER     0
+#define INTERRUPT_SPURIOUS  15
+#define EOI 0        /**< The actual value doesn't matter. */
+extern void external_interrupt(void);
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/pal/pal.h
 ,0 → 1,91
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_PAL_H__
+#define __ia64_PAL_H__
+#define PAL_OK       0  /**< Call completed without error. */
+#define PAL_UNIMPL  -1  /**< Unimplemented procedure. */
+#define PAL_INVARG  -2  /**< Invalid argument. */
+#define PAL_ERR     -3  /**< Can not compete call without error. */
+/** These are the indices for PAL_PROC. */
+#define PAL_CACHE_FLUSH     1
+#define PAL_CACHE_INFO      2
+#define PAL_CACHE_INIT      3
+#define PAL_CACHE_PROT_INFO 38
+#define PAL_CACHE_SHARED_INFO   43
+#define PAL_CACHE_SUMMARY   4
+#define PAL_MEM_ATTRIB      5
+#define PAL_PREFETCH_VISIBILITY 41
+#define PAL_PTCE_INFO       6
+#define PAL_VM_INFO     7
+#define PAL_VM_PAGE_SIZE    34
+#define PAL_VM_SUMMARY      8
+#define PAL_VM_TR_READ      261
+#define PAL_BUS_GET_FEATURES    9
+#define PAL_BUS_SET_FEATURES    10
+#define PAL_DEBUG_INFO      11
+#define PAL_FIXED_ADDR      12
+#define PAL_FREQ_BASE       13
+#define PAL_FREQ_RATIOS     14
+#define PAL_LOGICAL_TO_PHYSICAL 42
+#define PAL_PERF_MON_INFO   15
+#define PAL_PLATFORM_ADDR   16
+#define PAL_PROC_GET_FEATURES   17
+#define PAL_PROC_SET_FEATURES   18
+#define PAL_REGISTER_INFO   39
+#define PAL_RSE_INFO        19
+#define PAL_VERSION     20
+#define PAL_MC_CLEAR_LOG    21
+#define PAL_MC_DRAIN        22
+#define PAL_MC_DYNAMIC_STATE    24
+#define PAL_MC_ERROR_INFO   25
+#define PAL_MC_EXPECTED     23
+#define PAL_MC_REGISTER_MEM 27
+#define PAL_MC_RESUME       26
+#define PAL_HALT        28
+#define PAL_HALT_INFO       257
+#define PAL_HALT_LIGHT      29
+#define PAL_CACHE_LINE_INIT 31
+#define PAL_CACHE_READ      259
+#define PAL_CACHE_WRITE     260
+#define PAL_TEST_INFO       37
+#define PAL_TEST_PROC       258
+#define PAL_COPY_INFO       30
+#define PAL_COPY_PAL        256
+#define PAL_ENTER_IA_32_ENV 33
+#define PAL_PMI_ENTRYPOINT  32
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/types.h
 ,0 → 1,49
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __TYPES_H__
+#define __TYPES_H__
+#define NULL    0
+typedef signed char __s8;
+typedef unsigned char __u8;
+typedef unsigned short __u16;
+typedef unsigned int __u32;
+typedef unsigned long __u64;
+typedef __u64 __address;
+typedef __u64 ipl_t;
+typedef __u64 __native;
+typedef __u64 pte_t;
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/asm.h
 ,0 → 1,232
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_ASM_H__
+#define __ia64_ASM_H__
+#include <arch/types.h>
+#include <config.h>
+#include <arch/register.h>
+/** Return base address of current stack
+ *
+ * Return the base address of the current stack.
+ * The stack is assumed to be STACK_SIZE long.
+ * The stack must start on page boundary.
+ */
+static inline __address get_stack_base(void)
+{
+    __u64 v;
+    __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
+    return v;
+}
+/** Read IVR (External Interrupt Vector Register).
+ *
+ * @return Highest priority, pending, unmasked external interrupt vector.
+ */
+static inline __u64 ivr_read(void)
+{
+    __u64 v;
+    __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v));
+    return v;
+}
+/** Write ITC (Interval Timer Counter) register.
+ *
+ * @param New counter value.
+ */
+static inline void itc_write(__u64 v)
+{
+    __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v));
+}
+/** Read ITC (Interval Timer Counter) register.
+ *
+ * @return Current counter value.
+ */
+static inline __u64 itc_read(void)
+{
+    __u64 v;
+    __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v));
+    return v;
+}
+/** Write ITM (Interval Timer Match) register.
+ *
+ * @param New match value.
+ */
+static inline void itm_write(__u64 v)
+{
+    __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v));
+}
+/** Read ITV (Interval Timer Vector) register.
+ *
+ * @return Current vector and mask bit.
+ */
+static inline __u64 itv_read(void)
+{
+    __u64 v;
+    __asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v));
+    return v;
+}
+/** Write ITV (Interval Timer Vector) register.
+ *
+ * @param New vector and mask bit.
+ */
+static inline void itv_write(__u64 v)
+{
+    __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v));
+}
+/** Write EOI (End Of Interrupt) register.
+ *
+ * @param This value is ignored.
+ */
+static inline void eoi_write(__u64 v)
+{
+    __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v));
+}
+/** Read TPR (Task Priority Register).
+ *
+ * @return Current value of TPR.
+ */
+static inline __u64 tpr_read(void)
+{
+    __u64 v;
+    __asm__ volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
+    return v;
+}
+/** Write TPR (Task Priority Register).
+ *
+ * @param New value of TPR.
+ */
+static inline void tpr_write(__u64 v)
+{
+    __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v));
+}
+/** Disable interrupts.
+ *
+ * Disable interrupts and return previous
+ * value of PSR.
+ *
+ * @return Old interrupt priority level.
+ */
+static ipl_t interrupts_disable(void)
+{
+    __u64 v;
+    __asm__ volatile (
+        "mov %0 = psr\n"
+        "rsm %1\n"
+        : "=r" (v)
+        : "i" (PSR_I_MASK)
+    );
+    return (ipl_t) v;
+}
+/** Enable interrupts.
+ *
+ * Enable interrupts and return previous
+ * value of PSR.
+ *
+ * @return Old interrupt priority level.
+ */
+static ipl_t interrupts_enable(void)
+{
+    __u64 v;
+    __asm__ volatile (
+        "mov %0 = psr\n"
+        "ssm %1\n"
+        ";;\n"
+        "srlz.d\n"
+        : "=r" (v)
+        : "i" (PSR_I_MASK)
+    );
+    return (ipl_t) v;
+}
+/** Restore interrupt priority level.
+ *
+ * Restore PSR.
+ *
+ * @param ipl Saved interrupt priority level.
+ */
+static inline void interrupts_restore(ipl_t ipl)
+{
+    __asm__ volatile (
+        "mov psr.l = %0\n"
+        ";;\n"
+        "srlz.d\n"
+        : : "r" ((__u64) ipl)
+    );
+}
+/** Return interrupt priority level.
+ *
+ * @return PSR.
+ */
+static inline ipl_t interrupts_read(void)
+{
+    __u64 v;
+    __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
+    return (ipl_t) v;
+}
+#define set_shadow_register(reg,val) {__u64 v = val; __asm__  volatile("mov r15 = %0;;\n""bsw.0;;\n""mov "   #reg   " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); }
+#define get_shadow_register(reg,val) {__u64 v ; __asm__  volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
+#define get_control_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = cr" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
+#define get_aplication_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
+#define get_psr(val) {__u64 v ; __asm__  volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
+extern void cpu_halt(void);
+extern void cpu_sleep(void);
+extern void asm_delay_loop(__u32 t);
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/register.h
 ,0 → 1,72
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_REGISTER_H__
+#define __ia64_REGISTER_H__
+#include <arch/types.h>
+#define CR_IVR_MASK 0xf
+#define PSR_I_MASK  0x4000
+/** External Interrupt Vector Register */
+union cr_ivr {
+    __u8  vector;
+    __u64 value;
+};
+typedef union cr_ivr cr_ivr_t;
+/** Task Priority Register */
+union cr_tpr {
+    struct {
+        unsigned : 4;
+        unsigned mic: 4;        /**< Mask Interrupt Class. */
+        unsigned : 8;
+        unsigned mmi: 1;        /**< Mask Maskable Interrupts. */
+    } __attribute__ ((packed));
+    __u64 value;
+};
+typedef union cr_tpr cr_tpr_t;
+/** Interval Timer Vector */
+union cr_itv {
+    struct {
+        unsigned vector : 8;
+        unsigned : 4;
+        unsigned : 1;
+        unsigned : 3;
+        unsigned m : 1;         /**< Mask. */
+    } __attribute__ ((packed));
+    __u64 value;
+};
+typedef union cr_itv cr_itv_t;
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/barrier.h
 ,0 → 1,45
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_BARRIER_H__
+#define __ia64_BARRIER_H__
+/*
+ * TODO: Implement true IA-64 memory barriers for macros below.
+ */
+#define CS_ENTER_BARRIER()  memory_barrier()
+#define CS_LEAVE_BARRIER()  memory_barrier()
+#define memory_barrier()    __asm__ volatile ("mf\n" ::: "memory")
+#define read_barrier()      memory_barrier()
+#define write_barrier()     memory_barrier()
+#define srlz_i()        __asm__ volatile (";; srlz.i ;;\n" ::: "memory")
+#define srlz_d()        __asm__ volatile (";; srlz.d\n" ::: "memory")
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/mm/page.h
 ,0 → 1,73
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_PAGE_H__
+#define __ia64_PAGE_H__
+#include <arch/types.h>
+#include <arch/mm/frame.h>
+#define PAGE_SIZE   FRAME_SIZE
+#define KA2PA(x)    (((__address) (x))-0x8000000000000000)
+#define PA2KA(x)    (((__address) (x))+0x8000000000000000)
+#define page_arch_init()    ;
+/*
+ * Implementation of generic 4-level page table interface.
+ * TODO: this is a fake implementation provided to satisfy the compiler
+ */
+#define PTL0_INDEX_ARCH(vaddr)  0
+#define PTL1_INDEX_ARCH(vaddr)  0
+#define PTL2_INDEX_ARCH(vaddr)  0
+#define PTL3_INDEX_ARCH(vaddr)  0
+#define GET_PTL0_ADDRESS_ARCH()         ((pte_t *) 0)
+#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *) 0)
+#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      ((pte_t *) 0)
+#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      ((pte_t *) 0)
+#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((pte_t *) 0)
+#define SET_PTL0_ADDRESS_ARCH(ptl0)
+#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)
+#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
+#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
+#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)
+#define GET_PTL1_FLAGS_ARCH(ptl0, i)        0
+#define GET_PTL2_FLAGS_ARCH(ptl1, i)        0
+#define GET_PTL3_FLAGS_ARCH(ptl2, i)        0
+#define GET_FRAME_FLAGS_ARCH(ptl3, i)       0
+#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)
+#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
+#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
+#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/mm/asid.h
 ,0 → 1,36
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_ASID_H__
+#define __ia64_ASID_H__
+typedef int asid_t;
+#define asid_get()  0
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/mm/vm.h
 ,0 → 1,45
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_VM_H__
+#define __ia64_VM_H__
+#include <arch/types.h>
+#define KERNEL_ADDRESS_SPACE_START_ARCH     (__address) 0x8000000000000000
+#define KERNEL_ADDRESS_SPACE_END_ARCH       (__address) 0xffffffffffffffff
+#define USER_ADDRESS_SPACE_START_ARCH       (__address) 0x0000000000000000
+#define USER_ADDRESS_SPACE_END_ARCH     (__address) 0x7fffffffffffffff
+#define UTEXT_ADDRESS_ARCH  0x0000000000001000
+#define USTACK_ADDRESS_ARCH (0x7fffffffffffffff-(PAGE_SIZE-1))
+#define UDATA_ADDRESS_ARCH  0x0000000001001000
+#define vm_install_arch(vm)
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/mm/tlb.h
 ,0 → 1,34
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_TLB_H__
+#define __ia64_TLB_H__
+#define tlb_init_arch()
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/mm/memory_init.h
 ,0 → 1,36
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_MEMORY_INIT_H__
+#define __ia64_MEMORY_INIT_H__
+#include <config.h>
+#define get_memory_size()   CONFIG_MEMORY_SIZE
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/mm/frame.h
 ,0 → 1,36
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_FRAME_H__
+#define __ia64_FRAME_H__
+#define FRAME_SIZE      (16*1024)
+extern void frame_arch_init(void);
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/memstr.h
 ,0 → 1,39
+/*
+ * Copyright (C) 2005 Sergey Bondari
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_MEMSTR_H__
+#define __ia64_MEMSTR_H__
+#define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt));
+extern void memsetw(__address dst, size_t cnt, __u16 x);
+extern void memsetb(__address dst, size_t cnt, __u8 x);
+extern int memcmp(__address src, __address dst, int cnt);
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/byteorder.h
 ,0 → 1,36
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_BYTEORDER_H__
+#define __ia64_BYTEORDER_H__
+/* IA-64 is little-endian */
+#define __native_le2host(n)     (n)
+#define __u64_le2host(n)        (n)
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/fmath.h
 ,0 → 1,64
+/*
+ * Copyright (C) 2005 Josef Cejka
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arch/types.h>
+#define FMATH_EXPONENT_BIAS 1023
+typedef unsigned char fmath_ld_descr_t[8];
+typedef union { double bf; unsigned char ldd[8]; }  fmath_ld_union_t;
+/**returns exponent in binary encoding*/
+signed short fmath_get_binary_exponent(double num);
+/**returns exponent in decimal encoding*/
+double fmath_get_decimal_exponent(double num);
+/**returns mantisa in binary encoding */
+__u64 fmath_get_binary_mantisa(double num) ;
+/** Function for extract integer part from double
+* @param num input value
+* @param intp integer part of num
+* @return non-integer part
+*/
+double fmath_fint(double num, double *intp);
+/** count base^exponent from positive exponent
+* @param base
+* @param exponent - Must be > 0.0
+* @return base^exponent or 0.0 (if exponent <=0.0)
+*/
+double fmath_dpow(double base, double exponent) ;
+/** return 1, if num is NaN */
+int fmath_is_nan(double num);
+/** return 1, if fmath is a infinity */
+int fmath_is_infinity(double num);

 /tags/0.1.0/SPARTAN/arch/ia64/include/arch.h
 ,0 → 1,32
+/*
+ * Copyright (C) 2005 Martin Decky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_ARCH_H__
+#define __ia64_ARCH_H__
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/cpu.h
 ,0 → 1,37
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_CPU_H__
+#define __ia64_CPU_H__
+#include <typedefs.h>
+struct cpu_arch {
+};
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/atomic.h
 ,0 → 1,45
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_ATOMIC_H__
+#define __ia64_ATOMIC_H__
+/*
+ * TODO: these are just placeholders for real implementations of atomic_inc and atomic_dec.
+ * WARNING: the following functions cause the code to be preemption-unsafe !!!
+ */
+static inline atomic_inc(volatile int *val) {
+    *val++;
+}
+static inline atomic_dec(volatile int *val) {
+    *val--;
+}
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/fpu_context.h
 ,0 → 1,39
+/*
+ * Copyright (C) 2005 Jakub Vana
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_FPU_CONTEXT_H__
+#define __ia64_FPU_CONTEXT_H__
+#include <arch/types.h>
+struct fpu_context {
+/* TODO: define IA-64 FPU context */
+};
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/ski/ski.h
 ,0 → 1,38
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __SKI_H__
+#define __SKI_H__
+#define SKI_INIT_CONSOLE    20
+#define SKI_PUTCHAR     31
+extern void ski_init_console(void);
+extern void ski_putchar(const char ch);
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/faddr.h
 ,0 → 1,56
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_FADDR_H__
+#define __ia64_FADDR_H__
+#include <arch/types.h>
+static __address FADDR(void (* fptr)(void));
+/**
+ *
+ * Calculate absolute address of function
+ * referenced by fptr pointer.
+ *
+ * @param fptr Function pointer.
+ *
+ */
+inline __address FADDR(void (* fptr)(void)) {
+    __address faddr;
+    __asm__(
+        "ld8 %0 = [%1]\n\t"
+        : "=r" (faddr)
+        : "r" (fptr)
+    );
+    return faddr;
+}
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/include/arg.h
 ,0 → 1,34
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __ia64_ARG_H__
+#define __ia64_ARG_H__
+#include <stdarg.h>
+#endif

/tags/0.1.0/SPARTAN/arch/ia64/include/smp/atomic.h
--- include/thread.h (nonexistent)
+++ include/thread.h (revision 1968)
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ia64_THREAD_H__
+#define __ia64_THREAD_H__
+
+#define ARCH_THREAD_DATA struct { } arch_thread_data;
+
+#endif

 /tags/0.1.0/SPARTAN/arch/ia64/src/ivt.S
 ,0 → 1,765
+#
+# Copyright (C) 2005 Jakub Vana
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#include <arch/stack.h>
+#define STACK_ITEMS     12
+#define STACK_FRAME_SIZE    ((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
+#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
+#error Memory stack must be 16-byte aligned.
+#endif
+/** Heavyweight interrupt handler
+ *
+ * This macro roughly follows steps from 1 to 19 described in
+ * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
+ *
+ * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
+ * This goal is achieved by using procedure calls after RSE becomes operational.
+ *
+ * Some steps are skipped (enabling and disabling interrupts).
+ * Some steps are not fully supported yet (e.g. interruptions
+ * from userspace and floating-point context).
+ */
+.macro HEAVYWEIGHT_HANDLER offs handler
+    .org IVT + \offs
+    /* 1. copy interrupt registers into bank 0 */
+    mov r24 = cr.iip
+    mov r25 = cr.ipsr
+    mov r26 = cr.iipa
+    mov r27 = cr.isr
+    mov r28 = cr.ifa
+    /* 2. preserve predicate register into bank 0 */
+    mov r29 = pr ;;
+    /* 3. switch to kernel memory stack */
+    /* TODO: support interruptions from userspace */
+    /* assume kernel stack */
+    /* 4. save registers in bank 0 into memory stack */
+    add r31 = -8, r12 ;;
+    add r12 = -STACK_FRAME_SIZE, r12 ;;
+    st8 [r31] = r29, -8 ;;  /* save predicate registers */
+    st8 [r31] = r24, -8 ;;  /* save cr.iip */
+    st8 [r31] = r25, -8 ;;  /* save cr.ipsr */
+    st8 [r31] = r26, -8 ;;  /* save cr.iipa */
+    st8 [r31] = r27, -8 ;;  /* save cr.isr */
+    st8 [r31] = r28, -8 ;;  /* save cr.ifa */
+    /* 5. RSE switch from interrupted context */
+        .auto
+    mov r24 = ar.rsc
+    mov r25 = ar.pfs
+    cover
+    mov r26 = cr.ifs
+    st8 [r31] = r24, -8 /* save ar.rsc */
+    st8 [r31] = r25, -8 /* save ar.pfs */
+    st8 [r31] = r26, -8 /* save ar.ifs */
+    and r30 = ~3, r24
+    mov ar.rsc = r30    /* place RSE in enforced lazy mode */
+    mov r27 = ar.rnat
+    mov r28 = ar.bspstore
+    /* assume kernel backing store */
+    mov ar.bspstore = r28
+    mov r29 = ar.bsp
+    st8 [r31] = r27, -8 /* save ar.rnat */
+    st8 [r31] = r28, -8 /* save ar.bspstore */
+    st8 [r31] = r29     /* save ar.bsp */
+    mov ar.rsc = r24    /* restore RSE's setting */
+    .explicit
+    /* the rest of the save-handler can be kept outside IVT */
+    movl r24 = \handler
+    mov r25 = b0
+    br.call.sptk.many rp = heavyweight_handler_inner
+:  mov b0 = r25
+    br heavyweight_handler_finalize
+.endm
+.global heavyweight_handler_inner
+heavyweight_handler_inner:
+    /*
+     * From this point, the rest of the interrupted context
+     * will be preserved in stacked registers and backing store.
+     */
+    alloc loc0 = ar.pfs, 0, 46, 0, 0 ;;
+    /* copy handler address (r24 from bank 0 will be invisible soon) */
+    mov loc1 = r24
+    /* 6. switch to bank 1 and reenable PSR.ic */
+    ssm 0x2000
+    bsw.1 ;;
+    srlz.d
+    /* 7. preserve branch and application registers */
+        mov loc2 = ar.unat
+    mov loc3 = ar.lc
+    mov loc4 = ar.ec
+    mov loc5 = ar.ccv
+    mov loc6 = ar.csd
+    mov loc7 = ar.ssd
+    mov loc8 = b0
+    mov loc9 = b1
+    mov loc10 = b2
+    mov loc11 = b3
+    mov loc12 = b4
+    mov loc13 = b5
+    mov loc14 = b6
+    mov loc15 = b7
+    /* 8. preserve general and floating-point registers */
+    /* TODO: save floating-point context */
+    mov loc16 = r1
+    mov loc17 = r2
+    mov loc18 = r3
+    mov loc19 = r4
+    mov loc20 = r5
+    mov loc21 = r6
+    mov loc22 = r7
+    mov loc23 = r8
+    mov loc24 = r9
+    mov loc25 = r10
+    mov loc26 = r11
+    /* skip r12 (stack pointer) */
+    mov loc27 = r13
+    mov loc28 = r14
+    mov loc29 = r15
+    mov loc30 = r16
+    mov loc31 = r17
+    mov loc32 = r18
+    mov loc33 = r19
+    mov loc34 = r20
+    mov loc35 = r21
+    mov loc36 = r22
+    mov loc37 = r23
+    mov loc38 = r24
+    mov loc39 = r25
+    mov loc40 = r26
+    mov loc41 = r27
+    mov loc42 = r28
+    mov loc43 = r29
+    mov loc44 = r30
+    mov loc45 = r31
+    /* 9. skipped (will not enable interrupts) */
+    /* 10. call handler */
+        mov b1 = loc1
+    br.call.sptk.many b0 = b1
+    /* 11. return from handler */
+:
+    /* 12. skipped (will not disable interrupts) */
+    /* 13. restore general and floating-point registers */
+    /* TODO: restore floating-point context */
+    mov r1 = loc16
+    mov r2 = loc17
+    mov r3 = loc18
+    mov r4 = loc19
+    mov r5 = loc20
+    mov r6 = loc21
+    mov r7 = loc22
+    mov r8 = loc23
+    mov r9 = loc24
+    mov r10 = loc25
+    mov r11 = loc26
+    /* skip r12 (stack pointer) */
+    mov r13 = loc27
+    mov r14 = loc28
+    mov r15 = loc29
+    mov r16 = loc30
+    mov r17 = loc31
+    mov r18 = loc32
+    mov r19 = loc33
+    mov r20 = loc34
+    mov r21 = loc35
+    mov r22 = loc36
+    mov r23 = loc37
+    mov r24 = loc38
+    mov r25 = loc39
+    mov r26 = loc40
+    mov r27 = loc41
+    mov r28 = loc42
+    mov r29 = loc43
+    mov r30 = loc44
+    mov r31 = loc45
+    /* 14. restore branch and application registers */
+        mov ar.unat = loc2
+    mov ar.lc = loc3
+    mov ar.ec = loc4
+    mov ar.ccv = loc5
+    mov ar.csd = loc6
+    mov ar.ssd = loc7
+    mov b0 = loc8
+    mov b1 = loc9
+    mov b2 = loc10
+    mov b3 = loc11
+    mov b4 = loc12
+    mov b5 = loc13
+    mov b6 = loc14
+    mov b7 = loc15
+    /* 15. disable PSR.ic and switch to bank 0 */
+    rsm 0x2000
+    bsw.0 ;;
+    srlz.d
+    mov ar.pfs = loc0
+    br.ret.sptk.many rp
+.global heavyweight_handler_finalize
+heavyweight_handler_finalize:
+    /* 16. RSE switch to interrupted context */
+/********************************************************************************************/
+    .auto
+    cover           /*Allocate zerro size frame (Step 1(from Intel Docs))*/
+    add r31 = STACK_SCRATCH_AREA_SIZE, r12
+    mov r28 = ar.bspstore   /*Calculate loadrs (step 2)*/
+    ld8 r29 = [r31], +8
+    sub r27 = r29 , r28
+    shl r27 = r27, 16
+    mov r24 = ar.rsc
+    and r30 = ~3, r24
+    or  r24 = r30 , r27
+    mov ar.rsc = r24    /* place RSE in enforced lazy mode */
+    loadrs          /*(Step 3)*/
+                /*Read saved registers*/
+    ld8 r28 = [r31], +8     /*ar.bspstore*/
+    ld8 r27 = [r31], +8     /*ar.rnat*/
+    ld8 r26 = [r31], +8     /*cr.ifs*/
+    ld8 r25 = [r31], +8     /*ar.pfs*/
+    ld8 r24 = [r31], +8     /*ar.rsc*/
+    mov ar.bspstore = r28   /*(Step 4)*/
+    mov ar.rnat = r27   /*(Step 5)*/
+    mov ar.pfs = r25    /*(Step 6)*/
+    mov cr.ifs = r26
+    mov ar.rsc = r24    /*(Step 7)*/
+    .explicit
+/********************************************************************************************/
+    /* 17. restore interruption state from memory stack */
+    ld8 r28 = [r31] , +8 ;; /* load cr.ifa */
+    ld8 r27 = [r31] , +8 ;; /* load cr.isr */
+    ld8 r26 = [r31] , +8 ;; /* load cr.iipa */
+    ld8 r25 = [r31] , +8 ;; /* load cr.ipsr */
+    ld8 r24 = [r31] , +8 ;; /* load cr.iip */
+    mov cr.iip = r24
+    mov cr.ipsr = r25
+    mov cr.iipa = r26
+    mov cr.isr = r27
+    mov cr.ifa = r28
+    /* 18. restore predicate registers from memory stack */
+    ld8 r29 = [r31] , -8 ;; /* load predicate registers */
+    mov pr =r29 ;;
+    add r12 = STACK_FRAME_SIZE,r12;;
+    /* 19. return from interruption */
+    rfi;;
+dump_gregs:
+mov r16 = REG_DUMP;;
+st8 [r16] = r0;;
+add r16 = 8,r16 ;;
+st8 [r16] = r1;;
+add r16 = 8,r16 ;;
+st8 [r16] = r2;;
+add r16 = 8,r16 ;;
+st8 [r16] = r3;;
+add r16 = 8,r16 ;;
+st8 [r16] = r4;;
+add r16 = 8,r16 ;;
+st8 [r16] = r5;;
+add r16 = 8,r16 ;;
+st8 [r16] = r6;;
+add r16 = 8,r16 ;;
+st8 [r16] = r7;;
+add r16 = 8,r16 ;;
+st8 [r16] = r8;;
+add r16 = 8,r16 ;;
+st8 [r16] = r9;;
+add r16 = 8,r16 ;;
+st8 [r16] = r10;;
+add r16 = 8,r16 ;;
+st8 [r16] = r11;;
+add r16 = 8,r16 ;;
+st8 [r16] = r12;;
+add r16 = 8,r16 ;;
+st8 [r16] = r13;;
+add r16 = 8,r16 ;;
+st8 [r16] = r14;;
+add r16 = 8,r16 ;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r16;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r17;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r18;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r19;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r20;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r21;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r22;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r23;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r24;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r25;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r26;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r27;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r28;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r29;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r30;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+bsw.1;;
+mov r15 = r31;;
+bsw.0;;
+st8 [r16] = r15;;
+add r16 = 8,r16 ;;
+st8 [r16] = r32;;
+add r16 = 8,r16 ;;
+st8 [r16] = r33;;
+add r16 = 8,r16 ;;
+st8 [r16] = r34;;
+add r16 = 8,r16 ;;
+st8 [r16] = r35;;
+add r16 = 8,r16 ;;
+st8 [r16] = r36;;
+add r16 = 8,r16 ;;
+st8 [r16] = r37;;
+add r16 = 8,r16 ;;
+st8 [r16] = r38;;
+add r16 = 8,r16 ;;
+st8 [r16] = r39;;
+add r16 = 8,r16 ;;
+st8 [r16] = r40;;
+add r16 = 8,r16 ;;
+st8 [r16] = r41;;
+add r16 = 8,r16 ;;
+st8 [r16] = r42;;
+add r16 = 8,r16 ;;
+st8 [r16] = r43;;
+add r16 = 8,r16 ;;
+st8 [r16] = r44;;
+add r16 = 8,r16 ;;
+st8 [r16] = r45;;
+add r16 = 8,r16 ;;
+st8 [r16] = r46;;
+add r16 = 8,r16 ;;
+st8 [r16] = r47;;
+add r16 = 8,r16 ;;
+st8 [r16] = r48;;
+add r16 = 8,r16 ;;
+st8 [r16] = r49;;
+add r16 = 8,r16 ;;
+st8 [r16] = r50;;
+add r16 = 8,r16 ;;
+st8 [r16] = r51;;
+add r16 = 8,r16 ;;
+st8 [r16] = r52;;
+add r16 = 8,r16 ;;
+st8 [r16] = r53;;
+add r16 = 8,r16 ;;
+st8 [r16] = r54;;
+add r16 = 8,r16 ;;
+st8 [r16] = r55;;
+add r16 = 8,r16 ;;
+st8 [r16] = r56;;
+add r16 = 8,r16 ;;
+st8 [r16] = r57;;
+add r16 = 8,r16 ;;
+st8 [r16] = r58;;
+add r16 = 8,r16 ;;
+st8 [r16] = r59;;
+add r16 = 8,r16 ;;
+st8 [r16] = r60;;
+add r16 = 8,r16 ;;
+st8 [r16] = r61;;
+add r16 = 8,r16 ;;
+st8 [r16] = r62;;
+add r16 = 8,r16 ;;
+st8 [r16] = r63;;
+add r16 = 8,r16 ;;
+st8 [r16] = r64;;
+add r16 = 8,r16 ;;
+st8 [r16] = r65;;
+add r16 = 8,r16 ;;
+st8 [r16] = r66;;
+add r16 = 8,r16 ;;
+st8 [r16] = r67;;
+add r16 = 8,r16 ;;
+st8 [r16] = r68;;
+add r16 = 8,r16 ;;
+st8 [r16] = r69;;
+add r16 = 8,r16 ;;
+st8 [r16] = r70;;
+add r16 = 8,r16 ;;
+st8 [r16] = r71;;
+add r16 = 8,r16 ;;
+st8 [r16] = r72;;
+add r16 = 8,r16 ;;
+st8 [r16] = r73;;
+add r16 = 8,r16 ;;
+st8 [r16] = r74;;
+add r16 = 8,r16 ;;
+st8 [r16] = r75;;
+add r16 = 8,r16 ;;
+st8 [r16] = r76;;
+add r16 = 8,r16 ;;
+st8 [r16] = r77;;
+add r16 = 8,r16 ;;
+st8 [r16] = r78;;
+add r16 = 8,r16 ;;
+st8 [r16] = r79;;
+add r16 = 8,r16 ;;
+st8 [r16] = r80;;
+add r16 = 8,r16 ;;
+st8 [r16] = r81;;
+add r16 = 8,r16 ;;
+st8 [r16] = r82;;
+add r16 = 8,r16 ;;
+st8 [r16] = r83;;
+add r16 = 8,r16 ;;
+st8 [r16] = r84;;
+add r16 = 8,r16 ;;
+st8 [r16] = r85;;
+add r16 = 8,r16 ;;
+st8 [r16] = r86;;
+add r16 = 8,r16 ;;
+st8 [r16] = r87;;
+add r16 = 8,r16 ;;
+st8 [r16] = r88;;
+add r16 = 8,r16 ;;
+st8 [r16] = r89;;
+add r16 = 8,r16 ;;
+st8 [r16] = r90;;
+add r16 = 8,r16 ;;
+st8 [r16] = r91;;
+add r16 = 8,r16 ;;
+st8 [r16] = r92;;
+add r16 = 8,r16 ;;
+st8 [r16] = r93;;
+add r16 = 8,r16 ;;
+st8 [r16] = r94;;
+add r16 = 8,r16 ;;
+st8 [r16] = r95;;
+add r16 = 8,r16 ;;
+st8 [r16] = r96;;
+add r16 = 8,r16 ;;
+st8 [r16] = r97;;
+add r16 = 8,r16 ;;
+st8 [r16] = r98;;
+add r16 = 8,r16 ;;
+st8 [r16] = r99;;
+add r16 = 8,r16 ;;
+st8 [r16] = r100;;
+add r16 = 8,r16 ;;
+st8 [r16] = r101;;
+add r16 = 8,r16 ;;
+st8 [r16] = r102;;
+add r16 = 8,r16 ;;
+st8 [r16] = r103;;
+add r16 = 8,r16 ;;
+st8 [r16] = r104;;
+add r16 = 8,r16 ;;
+st8 [r16] = r105;;
+add r16 = 8,r16 ;;
+st8 [r16] = r106;;
+add r16 = 8,r16 ;;
+st8 [r16] = r107;;
+add r16 = 8,r16 ;;
+st8 [r16] = r108;;
+add r16 = 8,r16 ;;
+st8 [r16] = r109;;
+add r16 = 8,r16 ;;
+st8 [r16] = r110;;
+add r16 = 8,r16 ;;
+st8 [r16] = r111;;
+add r16 = 8,r16 ;;
+st8 [r16] = r112;;
+add r16 = 8,r16 ;;
+st8 [r16] = r113;;
+add r16 = 8,r16 ;;
+st8 [r16] = r114;;
+add r16 = 8,r16 ;;
+st8 [r16] = r115;;
+add r16 = 8,r16 ;;
+st8 [r16] = r116;;
+add r16 = 8,r16 ;;
+st8 [r16] = r117;;
+add r16 = 8,r16 ;;
+st8 [r16] = r118;;
+add r16 = 8,r16 ;;
+st8 [r16] = r119;;
+add r16 = 8,r16 ;;
+st8 [r16] = r120;;
+add r16 = 8,r16 ;;
+st8 [r16] = r121;;
+add r16 = 8,r16 ;;
+st8 [r16] = r122;;
+add r16 = 8,r16 ;;
+st8 [r16] = r123;;
+add r16 = 8,r16 ;;
+st8 [r16] = r124;;
+add r16 = 8,r16 ;;
+st8 [r16] = r125;;
+add r16 = 8,r16 ;;
+st8 [r16] = r126;;
+add r16 = 8,r16 ;;
+st8 [r16] = r127;;
+add r16 = 8,r16 ;;
+br.ret.sptk.many b0;;
+.macro Handler o h
+.org IVT + \o
+br \h;;
+.endm
+.macro Handler2 o
+.org IVT + \o
+br.call.sptk.many b0 = dump_gregs;;
+mov r16 = \o ;;
+bsw.1;;
+br universal_handler;;
+.endm
+.global IVT
+.align 32768
+IVT:
+Handler2 0x0000
+Handler2 0x0400
+Handler2 0x0800
+Handler2 0x0c00
+Handler2 0x1000
+Handler2 0x1400
+Handler2 0x1800
+Handler2 0x1c00
+Handler2 0x2000
+Handler2 0x2400
+Handler2 0x2800
+Handler 0x2c00 break_instruction
+HEAVYWEIGHT_HANDLER 0x3000 external_interrupt   /* For external interrupt, heavyweight handler is used. */
+Handler2 0x3400
+Handler2 0x3800
+Handler2 0x3c00
+Handler2 0x4000
+Handler2 0x4400
+Handler2 0x4800
+Handler2 0x4c00
+Handler2 0x5000
+Handler2 0x5100
+Handler2 0x5200
+Handler2 0x5300
+#Handler 0x5400 general_exception
+Handler2 0x5400
+Handler2 0x5500
+Handler2 0x5600
+Handler2 0x5700
+Handler2 0x5800
+Handler2 0x5900
+Handler2 0x5a00
+Handler2 0x5b00
+Handler2 0x5c00
+Handler2 0x5d00
+Handler2 0x5e00
+Handler2 0x5f00
+Handler2 0x6000
+Handler2 0x6100
+Handler2 0x6200
+Handler2 0x6300
+Handler2 0x6400
+Handler2 0x6500
+Handler2 0x6600
+Handler2 0x6700
+Handler2 0x6800
+Handler2 0x6900
+Handler2 0x6a00
+Handler2 0x6b00
+Handler2 0x6c00
+Handler2 0x6d00
+Handler2 0x6e00
+Handler2 0x6f00
+Handler2 0x7000
+Handler2 0x7100
+Handler2 0x7200
+Handler2 0x7300
+Handler2 0x7400
+Handler2 0x7500
+Handler2 0x7600
+Handler2 0x7700
+Handler2 0x7800
+Handler2 0x7900
+Handler2 0x7a00
+Handler2 0x7b00
+Handler2 0x7c00
+Handler2 0x7d00
+Handler2 0x7e00
+Handler2 0x7f00
+.align 32768
+.global REG_DUMP
+REG_DUMP:
+.space 128*8

 /tags/0.1.0/SPARTAN/arch/ia64/src/interrupt.c
 ,0 → 1,58
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <arch/interrupt.h>
+#include <panic.h>
+#include <print.h>
+#include <arch/types.h>
+#include <arch/asm.h>
+#include <arch/barrier.h>
+#include <arch/register.h>
+#include <arch/drivers/it.h>
+#include <arch.h>
+void external_interrupt(void)
+{
+    cr_ivr_t ivr;
+    ivr.value = ivr_read();
+    srlz_d();
+    switch(ivr.vector) {
+        case INTERRUPT_TIMER:
+        it_interrupt();
+            break;
+        case INTERRUPT_SPURIOUS:
+            printf("cpu%d: spurious interrupt\n", CPU->id);
+        break;
+        default:
+        panic("\nUnhandled External Interrupt Vector %d\n", ivr.vector);
+        break;
+    }
+}

 /tags/0.1.0/SPARTAN/arch/ia64/src/ia64.c
 ,0 → 1,41
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arch.h>
+#include <arch/ski/ski.h>
+#include <arch/drivers/it.h>
+void arch_pre_mm_init(void)
+{
+    ski_init_console();
+    it_init();
+}
+void arch_post_mm_init(void)
+{
+}

 /tags/0.1.0/SPARTAN/arch/ia64/src/context.S
 ,0 → 1,196
+#
+# Copyright (C) 2005 Jakub Jermar
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+.text
+.global context_save_arch
+.global context_restore_arch
+context_save_arch:
+    alloc loc0 = ar.pfs, 1, 8, 0, 0
+    mov loc1 = ar.unat  ;;
+    /* loc2 */
+    mov loc3 = ar.rsc
+    .auto
+    /*
+     * Flush dirty registers to backing store.
+     * After this ar.bsp and ar.bspstore are equal.
+     */
+    flushrs
+    mov loc4 = ar.bsp
+    /*
+     * Put RSE to enforced lazy mode.
+     * So that ar.rnat can be read.
+     */
+    and loc5 = ~3, loc3
+    mov ar.rsc = loc5
+    mov loc5 = ar.rnat
+    .explicit
+    mov loc6 = ar.lc
+    /*
+     * Save application registers
+     */
+    st8 [in0] = loc0, 8 ;;  /* save ar.pfs */
+    st8 [in0] = loc1, 8 ;;  /* save ar.unat (caller) */
+    mov loc2 = in0      ;;
+    add in0 = 8, in0    ;;  /* skip ar.unat (callee) */
+    st8 [in0] = loc3, 8 ;;  /* save ar.rsc */
+    st8 [in0] = loc4, 8 ;;  /* save ar.bsp */
+    st8 [in0] = loc5, 8 ;;  /* save ar.rnat */
+    st8 [in0] = loc6, 8 ;;  /* save ar.lc */
+    /*
+     * Save general registers including NaT bits
+     */
+    st8.spill [in0] = r1, 8     ;;
+    st8.spill [in0] = r4, 8     ;;
+    st8.spill [in0] = r5, 8     ;;
+    st8.spill [in0] = r6, 8     ;;
+    st8.spill [in0] = r7, 8     ;;
+    st8.spill [in0] = r12, 8    ;;  /* save sp */
+    st8.spill [in0] = r13, 8    ;;
+    mov loc3 = ar.unat      ;;
+    st8 [loc2] = loc3       /* save ar.unat (callee) */
+    /*
+     * Save branch registers
+     */
+    mov loc2 = b0       ;;
+    st8 [in0] = loc2, 8     /* save pc */
+    mov loc3 = b1       ;;
+    st8 [in0] = loc3, 8
+    mov loc4 = b2       ;;
+    st8 [in0] = loc4, 8
+    mov loc5 = b3       ;;
+    st8 [in0] = loc5, 8
+    mov loc6 = b4       ;;
+    st8 [in0] = loc6, 8
+    mov loc7 = b5       ;;
+    st8 [in0] = loc7, 8
+    /*
+     * Save predicate registers
+     */
+    mov loc2 = pr       ;;
+    st8 [in0] = loc2, 8
+    mov ar.unat = loc1
+    add r8 = r0, r0, 1      /* context_save returns 1 */
+    br.ret.sptk.many b0
+context_restore_arch:
+    alloc loc0 = ar.pfs, 1, 9, 0, 0 ;;
+    ld8 loc0 = [in0], 8 ;;  /* load ar.pfs */
+    ld8 loc1 = [in0], 8 ;;  /* load ar.unat (caller) */
+    ld8 loc2 = [in0], 8 ;;  /* load ar.unat (callee) */
+    ld8 loc3 = [in0], 8 ;;  /* load ar.rsc */
+    ld8 loc4 = [in0], 8 ;;  /* load ar.bsp */
+    ld8 loc5 = [in0], 8 ;;  /* load ar.rnat */
+    ld8 loc6 = [in0], 8 ;;  /* load ar.lc */
+    .auto
+    /*
+     * Invalidate the ALAT
+     */
+    invala
+    /*
+     * Put RSE to enforced lazy mode.
+     * So that ar.bspstore and ar.rnat can be written.
+     */
+    movl loc8 = ~3
+    and loc8 = loc3, loc8
+    mov ar.rsc = loc8
+    /*
+     * Flush dirty registers to backing store.
+     * We do this because we want the following move
+     * to ar.bspstore to assign the same value to ar.bsp.
+     */
+    flushrs
+    /*
+     * Restore application registers
+     */
+    mov ar.bspstore = loc4  /* rse.bspload = ar.bsp = ar.bspstore = loc4 */
+    mov ar.rnat = loc5
+    mov ar.pfs = loc0
+    mov ar.rsc = loc3
+    .explicit
+    mov ar.unat = loc2  ;;
+    mov ar.lc = loc6
+    /*
+     * Restore general registers including NaT bits
+     */
+    ld8.fill r1 = [in0], 8  ;;
+    ld8.fill r4 = [in0], 8  ;;
+    ld8.fill r5 = [in0], 8  ;;
+    ld8.fill r6 = [in0], 8  ;;
+    ld8.fill r7 = [in0], 8  ;;
+    ld8.fill r12 = [in0], 8 ;;  /* restore sp */
+    ld8.fill r13 = [in0], 8 ;;
+    /*
+     * Restore branch registers
+     */
+    ld8 loc2 = [in0], 8 ;;  /* restore pc */
+    mov b0 = loc2
+    ld8 loc3 = [in0], 8 ;;
+    mov b1 = loc3
+    ld8 loc4 = [in0], 8 ;;
+    mov b2 = loc4
+    ld8 loc5 = [in0], 8 ;;
+    mov b3 = loc5
+    ld8 loc6 = [in0], 8 ;;
+    mov b4 = loc6
+    ld8 loc7 = [in0], 8 ;;
+    mov b5 = loc7
+    /*
+     * Restore predicate registers
+     */
+    ld8 loc2 = [in0], 8 ;;
+    mov pr = loc2, ~0
+    mov ar.unat = loc1
+    mov r8 = r0         /* context_restore returns 0 */
+    br.ret.sptk.many b0

 /tags/0.1.0/SPARTAN/arch/ia64/src/drivers/it.c
 ,0 → 1,65
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** Interval Timer driver. */
+#include <arch/drivers/it.h>
+#include <arch/interrupt.h>
+#include <arch/register.h>
+#include <arch/asm.h>
+#include <arch/barrier.h>
+#include <time/clock.h>
+/** Initialize Interval Timer. */
+void it_init(void)
+{
+    cr_itv_t itv;
+    /* initialize Interval Timer external interrupt vector */
+    itv.value = itv_read();
+    itv.vector = INTERRUPT_TIMER;
+    itv.m = 0;
+    itv_write(itv.value);
+    srlz_d();
+    /* set Interval Timer Counter to zero */
+    itc_write(0);
+    srlz_d();
+    /* generate first Interval Timer interrupt in IT_DELTA ticks */
+    itm_write(IT_DELTA);
+    srlz_d();
+}
+/** Process Interval Timer interrupt. */
+void it_interrupt(void)
+{
+    eoi_write(EOI);
+    itm_write(itc_read() + IT_DELTA);   /* program next interruption */
+    clock();
+}

 /tags/0.1.0/SPARTAN/arch/ia64/src/dummy.s
 ,0 → 1,58
+#
+# Copyright (C) 2005 Jakub Jermar
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+.text
+.global calibrate_delay_loop
+.global asm_delay_loop
+.global userspace
+.global before_thread_runs_arch
+.global arch_late_init
+.global cpu_identify
+.global cpu_print_report
+.global cpu_sleep
+.global dummy
+.global fpu_enable
+.global fpu_disable
+.global fpu_init
+before_thread_runs_arch:
+userspace:
+calibrate_delay_loop:
+asm_delay_loop:
+arch_late_init:
+cpu_identify:
+cpu_print_report:
+cpu_sleep:
+fpu_init:
+fpu_enable:
+fpu_disable:
+dummy:
+    br.ret.sptk.many b0

 /tags/0.1.0/SPARTAN/arch/ia64/src/start.S
 ,0 → 1,74
+#
+# Copyright (C) 2005 Jakub Jermar
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+.section K_TEXT_START
+.global kernel_image_start
+stack0:
+kernel_image_start:
+    .auto
+    # initialize PSR
+    mov psr.l = r0
+    srlz.i
+    srlz.d
+    # initialize register stack
+    mov ar.rsc = r0
+    mov ar.bspstore = r0
+    loadrs
+    .explicit
+    # initialize memory stack to some sane value
+    movl r12 = stack0   ;;
+    add r12 = - 16, r12 /* allocate a scratch area on the stack */
+    # initialize gp (Global Pointer) register
+    movl r1 = _hardcoded_load_address
+    ;;
+    #
+    # Initialize hardcoded_* variables.
+    #
+    movl r14 = _hardcoded_ktext_size
+    movl r15 = _hardcoded_kdata_size
+    movl r16 = _hardcoded_load_address
+    addl r17 = @gprel(hardcoded_ktext_size), gp
+    addl r18 = @gprel(hardcoded_kdata_size), gp
+    addl r19 = @gprel(hardcoded_load_address), gp
+    ;;
+    st4 [r17] = r14
+    st4 [r18] = r15
+    st8 [r19] = r16
+    br.call.sptk.many b0=main_bsp
+:
+    br 0b

 /tags/0.1.0/SPARTAN/arch/ia64/src/interrupt_handler.c
 ,0 → 1,209
+/*
+ * Copyright (C) 2005 Jakub Vana
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <panic.h>
+#include <print.h>
+#include <arch/types.h>
+#include <arch/asm.h>
+#include <symtab.h>
+#include <debug.h>
+#define VECTORS_64_BUNDLE   20
+#define VECTORS_16_BUNDLE   48
+#define VECTORS_16_BUNDLE_START 0x5000
+#define VECTOR_MAX      0x7f00
+#define BUNDLE_SIZE     16
+extern __u64 REG_DUMP;
+char *vector_names_64_bundle[VECTORS_64_BUNDLE] = {
+    "VHPT Translation vector",
+    "Instruction TLB vector",
+    "Data TLB vector",
+    "Alternate Instruction TLB vector",
+    "Alternate Data TLB vector",
+    "Data Nested TLB vector",
+    "Instruction Key Miss vector",
+    "Data Key Miss vector",
+    "Dirty-Bit vector",
+    "Instruction Access-Bit vector",
+    "Data Access-Bit vector"
+    "Break Instruction vector",
+    "External Interrupt vector"
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "Reserved"
+};
+char *vector_names_16_bundle[VECTORS_16_BUNDLE] = {
+    "Page Not Present vector",
+    "Key Permission vector",
+    "Instruction Access rights vector",
+    "Data Access Rights vector",
+    "General Exception vector",
+    "Disabled FP-Register vector",
+    "NaT Consumption vector",
+    "Speculation vector",
+    "Reserved",
+    "Debug vector",
+    "Unaligned Reference vector",
+    "Unsupported Data Reference vector",
+    "Floating-point Fault vector",
+    "Floating-point Trap vector",
+    "Lower-Privilege Transfer Trap vector",
+    "Taken Branch Trap vector",
+    "Single STep Trap vector",
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "Reserved",
+    "IA-32 Exception vector",
+    "IA-32 Intercept vector",
+    "IA-32 Interrupt vector",
+    "Reserved",
+    "Reserved",
+    "Reserved"
+};
+static char *vector_to_string(__u16 vector);
+char *vector_to_string(__u16 vector)
+{
+    ASSERT(vector <= VECTOR_MAX);
+    if (vector >= VECTORS_16_BUNDLE_START)
+        return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)];
+    else
+        return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)];
+}
+void general_exception(void);
+void general_exception(void)
+{
+    panic("\nGeneral Exception\n");
+}
+void break_instruction(void);
+void break_instruction(void)
+{
+    panic("\nBreak Instruction\n");
+}
+#define cr_dump(r) {__u64 val; get_control_register(r,val); printf("\ncr"#r":%Q",val);}
+#define ar_dump(r) {__u64 val; get_aplication_register(r,val); printf("\nar"#r":%Q",val);}
+void universal_handler(void);
+void universal_handler(void)
+{
+    __u64 vector,psr,PC;
+    __u64 *p;
+    int i;
+    char *sym;
+    get_shadow_register(16,vector);
+    p=&REG_DUMP;
+    for(i=0;i<128;i+=2) printf("gr%d:%Q\tgr%d:%Q\n",i,p[i],i+1,p[i+1]);
+    cr_dump(0);
+    cr_dump(1);
+    cr_dump(2);
+    cr_dump(8);
+    cr_dump(16);
+    cr_dump(17);
+    cr_dump(19);get_control_register(19,PC); if(sym=get_symtab_entry(PC)) printf("(%s)",sym);
+    cr_dump(20);get_control_register(20,PC); if(sym=get_symtab_entry(PC)) printf("(%s)",sym);
+    cr_dump(21);
+    cr_dump(22);get_control_register(22,PC); if(sym=get_symtab_entry(PC)) printf("(%s)",sym);
+    cr_dump(23);
+    cr_dump(24);
+    cr_dump(25);
+    cr_dump(64);
+    cr_dump(65);
+    cr_dump(66);
+    cr_dump(67);
+    cr_dump(68);
+    cr_dump(69);
+    cr_dump(70);
+    cr_dump(71);
+    cr_dump(72);
+    cr_dump(73);
+    cr_dump(74);
+    cr_dump(80);
+    cr_dump(81);
+    ar_dump(0);
+    ar_dump(1);
+    ar_dump(2);
+    ar_dump(3);
+    ar_dump(4);
+    ar_dump(5);
+    ar_dump(6);
+    ar_dump(7);
+    ar_dump(16);
+    ar_dump(17);
+    ar_dump(18);
+    ar_dump(19);
+    ar_dump(21);
+    ar_dump(24);
+    ar_dump(25);
+    ar_dump(26);
+    ar_dump(27);
+    ar_dump(28);
+    ar_dump(29);
+    ar_dump(30);
+    ar_dump(32);
+    ar_dump(36);
+    ar_dump(40);
+    ar_dump(44);
+    ar_dump(64);
+    ar_dump(65);
+    ar_dump(66);
+    get_psr(psr);
+    printf("\nPSR:%Q\n",psr);
+    panic("\nException:%W (%s)\n", (__u16) vector, vector_to_string(vector));
+}

 /tags/0.1.0/SPARTAN/arch/ia64/src/mm/frame.c
 ,0 → 1,43
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arch/mm/frame.h>
+#include <mm/frame.h>
+#include <config.h>
+#include <panic.h>
+void frame_arch_init(void)
+{
+    zone_t *z;
+    z = zone_create(0, config.memory_size, 0);
+    if (!z) {
+        panic("Can't allocate zone (%dB).\n", config.memory_size);
+    }
+    zone_attach(z);
+}

 /tags/0.1.0/SPARTAN/arch/ia64/src/fpu_context.c
 ,0 → 1,40
+/*
+ * Copyright (C) 2005 Jakub Vana
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <fpu_context.h>
+void fpu_context_save(fpu_context_t *fctx)
+{
+}
+void fpu_context_restore(fpu_context_t *fctx)
+{
+}

 /tags/0.1.0/SPARTAN/arch/ia64/src/cpu/cpu.c
 ,0 → 1,43
+#include <cpu.h>
+#include <print.h>
+#include <panic.h>
+#include <arch/types.h>
+extern int IVT;
+void cpu_arch_init(void)
+{
+    int *p=&IVT;
+    volatile __u64 hlp,hlp2;
+    int psr = 0x2000;
+    __asm__  volatile (
+        "mov cr2 = %0;;\n"
+        "{mov psr.l = %1;;}\n"
+        "{srlz.i;"
+        "srlz.d;;}"
+        :
+        : "r" (p), "r" (psr)
+    );
+    /*Switch register bank of regs r16 .. r31 to 1 It is automaticly cleared on exception*/
+    __asm__ volatile
+    (
+        "bsw.1;;\n"
+    );
+}

 /tags/0.1.0/SPARTAN/arch/ia64/src/fmath.c
 ,0 → 1,161
+/*
+ * Copyright (C) 2005 Josef Cejka
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arch/fmath.h>
+#include <print.h>
+    //TODO:
+#define FMATH_MANTISA_MASK ( 0x000fffffffffffffLL )
+signed short fmath_get_binary_exponent(double num)
+{   //TODO:
+/*  fmath_ld_union_t fmath_ld_union;
+    fmath_ld_union.bf = num;
+    return (signed short)((((fmath_ld_union.ldd[7])&0x7f)<<4) + (((fmath_ld_union.ldd[6])&0xf0)>>4)) -FMATH_EXPONENT_BIAS; // exponent is 11 bits lenght, so sevent bits is in 8th byte and 4 bits in 7th
+*/
+    return 0;
+}
+double fmath_get_decimal_exponent(double num)
+{   //TODO:
+    double value;
+    // log10(2)*log2(x) => log10(x)
+/*  __asm__ __volatile__ ( \
+    "fldlg2     #load log10(2)  \n\t"   \
+    "fxch %%st(1)       \n\t" \
+    "fyl2x      #count st(0)*log2(st(1))->st(1); pop st(0)  \n\t" \
+    : "=t" (value) : "0"(num) );
+*/  return value;
+}
+__u64 fmath_get_binary_mantisa(double num)
+{   //TODO:
+/*  union { __u64 _u; double _d;} un = { _d : num };
+    un._u=un._u &(FMATH_MANTISA_MASK); // mask 52 bits of mantisa
+    return un._u;
+    */
+    return 0;
+}
+double fmath_fint(double num, double *intp)
+{   //TODO:
+/*  fmath_ld_union_t fmath_ld_union_num;
+    fmath_ld_union_t fmath_ld_union_int;
+    signed short exp;
+    __u64 mask,mantisa;
+    int i;
+    exp=fmath_get_binary_exponent(num);
+    if (exp<0) {
+        *intp = 0.0;
+        *intp = fmath_set_sign(0.0L,fmath_is_negative(num));
+        return num;
+        }
+    if (exp>51) {
+        *intp=num;
+        num=0.0;
+        num= fmath_set_sign(0.0L,fmath_is_negative(*intp));
+        return num;
+    }
+    fmath_ld_union_num.bf = num;
+    mask = FMATH_MANTISA_MASK>>exp;
+    //mantisa = (fmath_get-binary_mantisa(num))&(~mask);
+    for (i=0;i<7;i++) {
+        // Ugly construction for obtain sign, exponent and integer part from num
+        fmath_ld_union_int.ldd[i]=fmath_ld_union_num.ldd[i]&(((~mask)>>(i*8))&0xff);
+    }
+    fmath_ld_union_int.ldd[6]|=((fmath_ld_union_num.ldd[6])&(0xf0));
+    fmath_ld_union_int.ldd[7]=fmath_ld_union_num.ldd[7];
+    *intp=fmath_ld_union_int.bf;
+    return fmath_ld_union_num.bf-fmath_ld_union_int.bf;
+*/
+    return 0.0;
+};
+double fmath_dpow(double base, double exponent)
+{   //TODO:
+/*  double value=1.0;
+    if (base<=0.0) return base;
+    //2^(x*log2(10)) = 2^y = 10^x
+    __asm__ __volatile__ (      \
+        "fyl2x # ST(1):=ST(1)*log2(ST(0)), pop st(0) \n\t "     \
+        "fld    %%st(0) \n\t"   \
+        "frndint \n\t"      \
+        "fxch %%st(1) \n\t"     \
+        "fsub %%st(1),%%st(0) \n\t" \
+        "f2xm1  # ST := 2^ST -1\n\t"            \
+        "fld1 \n\t"         \
+        "faddp %%st(0),%%st(1) \n\t"    \
+        "fscale #ST:=ST*2^(ST(1))\n\t"      \
+        "fstp %%st(1) \n\t"     \
+    "" : "=t" (value) :  "0" (base), "u" (exponent) );
+    return value;
+*/
+    return 1.0;
+}
+int fmath_is_nan(double num)
+{
+/*  __u16 exp;
+    fmath_ld_union_t fmath_ld_union;
+    fmath_ld_union.bf = num;
+    exp=(((fmath_ld_union.ldd[7])&0x7f)<<4) + (((fmath_ld_union.ldd[6])&0xf0)>>4); // exponent is 11 bits lenght, so sevent bits is in 8th byte and 4 bits in 7th
+    if (exp!=0x07ff) return 0;
+    if (fmath_get_binary_mantisa(num)>=FMATH_NAN) return 1;
+*/
+    return 0;
+}
+int fmath_is_infinity(double num)
+{
+/*  __u16 exp;
+    fmath_ld_union_t fmath_ld_union;
+    fmath_ld_union.bf = num;
+    exp=(((fmath_ld_union.ldd[7])&0x7f)<<4) + (((fmath_ld_union.ldd[6])&0xf0)>>4); // exponent is 11 bits lenght, so sevent bits is in 8th byte and 4 bits in 7th
+    if (exp!=0x07ff) return 0;
+    if (fmath_get_binary_mantisa(num)==0x0) return 1;
+*/  return 0;
+}

 /tags/0.1.0/SPARTAN/arch/ia64/src/asm.S
 ,0 → 1,48
+#
+# Copyright (C) 2005 Jakub Jermar
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+.text
+.global memcpy
+memcpy:
+    br _memcpy
+.global memsetb
+memsetb:
+    br _memsetb
+.global cpu_halt
+cpu_halt:
+    br cpu_halt
+.global panic_printf
+panic_printf:
+    {
+        br.call.sptk.many b0=printf
+    }
+    br cpu_halt

 /tags/0.1.0/SPARTAN/arch/ia64/src/ski/ski.c
 ,0 → 1,66
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <arch/ski/ski.h>
+/** Initialize debug console
+ *
+ * Issue SSC (Simulator System Call) to
+ * to open debug console.
+ */
+void ski_init_console(void)
+{
+    __asm__ (
+        "mov r15=%0\n"
+        "break 0x80000\n"
+        :
+        : "i" (SKI_INIT_CONSOLE)
+        : "r15", "r8"
+    );
+}
+/** Display character on debug console
+ *
+ * Use SSC (Simulator System Call) to
+ * display character on debug console.
+ *
+ * @param ch   Character to be printed.
+ */
+void ski_putchar(const char ch)
+{
+    __asm__ (
+        "mov r15=%0\n"
+        "mov r32=%1\n"      /* r32 is in0 */
+        "break 0x80000\n"   /* modifies r8 */
+        :
+        : "i" (SKI_PUTCHAR), "r" (ch)
+        : "r15", "in0", "r8"
+    );
+    if (ch == '\n') ski_putchar('\r');
+}

 /tags/0.1.0/SPARTAN/arch/ia64/src/putchar.c
 ,0 → 1,35
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <putchar.h>
+#include <arch/ski/ski.h>
+void putchar(const char ch)
+{
+    ski_putchar(ch);
+}

 /tags/0.1.0/SPARTAN/arch/ia64/Makefile.inc
 ,0 → 1,38
+IA-64_TARGET=ia64-pc-linux-gnu
+IA-64_CC_DIR=/usr/local/ia64/bin
+IA-64_BINUTILS_DIR=/usr/local/ia64/bin
+CC=$(IA-64_CC_DIR)/$(IA-64_TARGET)-gcc
+AS=$(IA-64_BINUTILS_DIR)/$(IA-64_TARGET)-as
+LD=$(IA-64_BINUTILS_DIR)/$(IA-64_TARGET)-ld
+OBJDUMP=$(IA-64_BINUTILS_DIR)/$(IA-64_TARGET)-objdump
+OBJCOPY=$(IA-64_BINUTILS_DIR)/$(IA-64_TARGET)-objcopy
+BFD_NAME=elf64-little
+BFD_ARCH=ia64-elf64
+ASFLAGS=-mconstant-gp
+DEFS=-DARCH=$(ARCH)
+CFLAGS=$(DEFS) -mconstant-gp -nostdlib -fno-builtin -fno-unwind-tables -O3
+LFLAGS=-EL -M
+arch_sources= \
+    generic/src/arch/start.S \
+    generic/src/arch/asm.S \
+    generic/src/arch/dummy.s \
+    generic/src/arch/putchar.c \
+    generic/src/arch/ia64.c \
+    generic/src/arch/fpu_context.c \
+    generic/src/arch/context.S \
+    generic/src/arch/ski/ski.c \
+    generic/src/arch/cpu/cpu.c \
+    generic/src/arch/ivt.S \
+    generic/src/arch/interrupt.c \
+    generic/src/arch/interrupt_handler.c \
+    generic/src/arch/fmath.c \
+    generic/src/arch/mm/frame.c \
+    generic/src/arch/drivers/it.c

 /tags/0.1.0/SPARTAN/arch/ia64/boot/Makefile
 ,0 → 1,24
+IA-64_BINUTILS_DIR=/usr/local/ia64/bin
+IA-64_TARGET=ia64-pc-linux-gnu
+.PHONY: nothing build
+nothing:
+build: boot.bin
+    cp boot.bin ../../../load.bin
+AS=$(IA-64_BINUTILS_DIR)/$(IA-64_TARGET)-as
+LD=$(IA-64_BINUTILS_DIR)/$(IA-64_TARGET)-ld
+ASFLAGS=-EL
+LFLAGS=-EL -T _link.ld -n
+boot.bin: boot.o
+    $(LD) $(LFLAGS) boot.o -o $@
+boot.o:
+    $(AS) boot.s -o $@
+clean:
+    -rm *.o *.bin

 /tags/0.1.0/SPARTAN/arch/ia64/boot/_link.ld
 ,0 → 1,72
+OUTPUT_FORMAT(elf64-ia64-little)
+ENTRY(start)
+SECTIONS {
+    .image 0x0000000000000000: AT (0x0000000000000000) {
+        *(.text .stub .text.* .gnu.linkonce.t.*)
+        *(.interp)
+        *(.hash)
+        *(.dynsym)
+        *(.dynstr)
+        *(.rel.init)
+        *(.rela.init)
+        *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+        *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+        *(.rel.fini)
+        *(.rela.fini)
+        *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+        *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+        *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+        *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+        *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+        *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+        *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+        *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+        *(.rel.got)
+        *(.rela.got)
+        *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+        *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+        *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+        *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+        *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+        *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+        *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+        *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+        *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+        *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+        *(.rel.plt)
+        *(.rela.plt)
+        *(.rela.IA_64.pltoff)
+        *(.init)
+        *(.plt)
+        *(.fini)
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        *(.rodata1)
+        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+        *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+        *(.opd)
+        *(.IA_64.unwind_info* .gnu.linkonce.ia64unwi.*)
+        *(.IA_64.unwind* .gnu.linkonce.ia64unw.*)
+        *(.eh_frame_hdr)
+        *(.preinit_array)
+        *(.init_array)
+        *(.fini_array)
+        *(.data .data.* .gnu.linkonce.d.*)
+        *(.data1)
+        *(.tdata .tdata.* .gnu.linkonce.td.*)
+        *(.tcommon)
+        *(.eh_frame)
+        *(.gcc_except_table)
+        *(.dynamic)
+        *(.jcr)
+        *(.got)
+        *(.IA_64.pltoff)
+        *(.sdata .sdata.* .gnu.linkonce.s.*)
+        *(.dynsbss)
+        *(.sbss .sbss.* .gnu.linkonce.sb.*)
+        *(.scommon)
+        *(.dynbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+    }
+}

 /tags/0.1.0/SPARTAN/arch/ia64/boot/boot.s
 ,0 → 1,33
+#
+# Copyright (C) 2005 Jakub Jermar
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+.text
+.global start
+start:
+    brl 0x0000000000001000

 /tags/0.1.0/SPARTAN/arch/ia64/_link.ld
 ,0 → 1,42
+/*
+ *  IA-64 linker script
+ *
+ *  It is ELF format, but its only section looks like this:
+ *  kernel text
+ *  kernel data
+ *
+ */
+OUTPUT_FORMAT(elf64-ia64-little)
+ENTRY(kernel_image_start)
+SECTIONS {
+    .image 0x0000000000001000: AT (0x0000000000001000) {
+        ktext_start = .;
+        *(K_TEXT_START);
+        *(.text)
+        ktext_end = .;
+        kdata_start = .;
+        *(K_DATA_START)
+        *(.rodata .rodata.*)
+        *(.opd)
+        *(.data)
+        *(.got .got.*)
+        *(.sdata)
+        *(.sbss)
+        *(.scommon)
+        *(.bss)
+        *(COMMON);
+                symbol_table = .;
+                *(symtab.*);            /* Symbol table, must be LAST symbol!*/
+        kdata_end = .;
+    }
+    _hardcoded_ktext_size = ktext_end - ktext_start;
+    _hardcoded_kdata_size = kdata_end - kdata_start;
+    _hardcoded_load_address = 0x0000000000001000;
+}

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