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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /kernel @ 747

  → /kernel @ 748

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 747 → Rev 748

/kernel/trunk/arch/ia64/include/mm/page.h
46,8 → 46,8
#define SET_PTL0_ADDRESS_ARCH(ptl0)
/** Implementation of page hash table interface. */
#define HT_ENTRIES_ARCH 0
#define HT_HASH_ARCH(page, asid) 0
#define HT_ENTRIES_ARCH (VHPT_SIZE/sizeof(pte_t))
#define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid))
#define HT_COMPARE_ARCH(page, asid, t) 0
#define HT_SLOT_EMPTY_ARCH(t) 1
#define HT_INVALIDATE_SLOT_ARCH(t)
55,7 → 55,11
#define HT_SET_NEXT_ARCH(t, s)
#define HT_SET_RECORD_ARCH(t, page, asid, frame, flags)
#define VRN_SHIFT 61
#define VRN_MASK (7LL << VRN_SHIFT)
#define VRN_KERNEL 0
#define VRN_WORK 1LL
#define REGION_REGISTERS 8
#define VHPT_WIDTH 20 /* 1M */
197,7 → 201,7
{
__u64 ret;
// ASSERT(i < REGION_REGISTERS);
ASSERT(i < REGION_REGISTERS);
__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
return ret;
211,7 → 215,7
*/
static inline void rr_write(index_t i, __u64 v)
{
// ASSERT(i < REGION_REGISTERS);
ASSERT(i < REGION_REGISTERS);
__asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v));
}
238,5 → 242,6
}
extern void page_arch_init(void);
extern pte_t *vhpt_hash(__address page, asid_t asid);
#endif

/kernel/trunk/arch/ia64/src/mm/page.c
38,6 → 38,7
#include <panic.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <memstr.h>
/** Initialize VHPT and region registers. */
static void set_vhpt_environment(void)
66,6 → 67,7
continue;
rr.word == rr_read(i);
rr.map.ve = 0; /* disable VHPT walker */
rr.map.rid = ASID_INVALID;
rr_write(i, rr.word);
srlz_i();
76,7 → 78,8
* Allocate VHPT and invalidate all its entries.
*/
page_ht = (pte_t *) frame_alloc(FRAME_KA, VHPT_WIDTH - FRAME_WIDTH, NULL);
ht_invalidate_all();
memsetb((__address) page_ht, VHPT_SIZE, 0);
ht_invalidate_all();
/*
* Set up PTA register.
98,3 → 101,38
pk_disable();
set_vhpt_environment();
}
/** Calculate address of collision chain from VPN and ASID.
*
* This is rather non-trivial function.
* First, it has to translate ASID to RID.
* This is achieved by taking VRN bits of
* page into account.
* Second, it must preserve the region register
* it writes the RID to.
*
* @param page Address of virtual page including VRN bits.
* @param asid Address space identifier.
*
* @return Head of VHPT collision chain for page and asid.
*/
pte_t *vhpt_hash(__address page, asid_t asid)
{
region_register rr_save, rr;
pte_t *t;
rr_save.word = rr_read(VRN_WORK);
rr.word = rr_save.word;
if ((page >> VRN_SHIFT) != VRN_KERNEL)
rr.map.rid = (asid * RIDS_PER_ASID) + (page >> VRN_SHIFT);
else
rr.map.rid = ASID_KERNEL;
rr_write(VRN_WORK, rr.word);
srlz_i();
t = (pte_t *) thash((VRN_WORK << VRN_SHIFT) | (~(VRN_MASK) & page));
rr_write(VRN_WORK, rr_save.word);
srlz_i();
srlz_d();
return t;
}