8,6 → 8,7 |
@ "ppc32" PowerPC 32-bit |
@ "ppc64" PowerPC 64-bit |
@ "sparc64" Sun UltraSPARC |
@ "xen32" Xen 32-bit |
! ARCH (choice) |
|
# IA32 Compiler |
35,7 → 36,7 |
@ "athlon-xp" Athlon XP |
@ "athlon-mp" Athlon MP |
@ "prescott" Prescott |
! [ARCH=ia32] IA32_CPU (choice) |
! [ARCH=ia32|ARCH=xen32] IA32_CPU (choice) |
|
# MIPS Machine type |
@ "msim" MSIM Simulator |
46,7 → 47,7 |
! [ARCH=mips32] MIPS_MACHINE (choice) |
|
# Framebuffer support |
! [(ARCH=mips32&MIPS_MACHINE=lgxemul)|(ARCH=mips32&MIPS_MACHINE=bgxemul)|(ARCH=ia32)|(ARCH=amd64)] CONFIG_FB (y/n) |
! [(ARCH=mips32&MIPS_MACHINE=lgxemul)|(ARCH=mips32&MIPS_MACHINE=bgxemul)|(ARCH=ia32)|(ARCH=amd64)|(ARCH=xen32)] CONFIG_FB (y/n) |
|
# Framebuffer width |
@ "320" |
59,7 → 60,7 |
@ "1440" |
@ "1600" |
@ "2048" |
! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_WIDTH (choice) |
! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_FB=y] CONFIG_VESA_WIDTH (choice) |
|
# Framebuffer height |
@ "200" |
75,27 → 76,27 |
@ "1050" |
@ "1200" |
@ "1536" |
! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_HEIGHT (choice) |
! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_FB=y] CONFIG_VESA_HEIGHT (choice) |
|
# Framebuffer depth |
@ "8" |
@ "16" |
@ "24" |
! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_BPP (choice) |
! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_FB=y] CONFIG_VESA_BPP (choice) |
|
|
|
# Support for SMP |
! [ARCH=ia32|ARCH=amd64] CONFIG_SMP (y/n) |
! [ARCH=ia32|ARCH=amd64|ARCH=xen32] CONFIG_SMP (y/n) |
|
# Improved support for hyperthreading |
! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_HT (y/n) |
! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_SMP=y] CONFIG_HT (y/n) |
|
# Simics BIOS AP boot fix |
! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n) |
! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n) |
|
# Lazy FPU context switching |
! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64] CONFIG_FPU_LAZY (y/n) |
! [(ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64|ARCH=xen32] CONFIG_FPU_LAZY (y/n) |
|
# Power off on halt |
! [ARCH=ppc32] CONFIG_POWEROFF (n/y) |
109,10 → 110,10 |
! [CONFIG_DEBUG=y&CONFIG_SMP=y] CONFIG_DEBUG_SPINLOCK (y/n) |
|
# Watchpoint on rewriting AS with zero |
! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=ia32)] CONFIG_DEBUG_AS_WATCHPOINT (y/n) |
! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=ia32|ARCH=xen32)] CONFIG_DEBUG_AS_WATCHPOINT (y/n) |
|
# Save all interrupt registers |
! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=mips32|ARCH=ia32)] CONFIG_DEBUG_ALLREGS (y/n) |
! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=mips32|ARCH=ia32|ARCH=xen32)] CONFIG_DEBUG_ALLREGS (y/n) |
|
# Use VHPT |
! [ARCH=ia64] CONFIG_VHPT (y/n) |
130,8 → 131,8 |
@ "synch/rwlock5" Read write test 5 |
@ "synch/semaphore1" Semaphore test 1 |
@ "synch/semaphore2" Sempahore test 2 |
@ [ARCH=ia32|ARCH=amd64|ARCH=ia64] "fpu/fpu1" Intel fpu test 1 |
@ [ARCH=ia32|ARCH=amd64] "fpu/sse1" Intel Sse test 1 |
@ [ARCH=ia32|ARCH=amd64|ARCH=ia64|ARCH=xen32] "fpu/fpu1" Intel fpu test 1 |
@ [ARCH=ia32|ARCH=amd64|ARCH=xen32] "fpu/sse1" Intel Sse test 1 |
@ [ARCH=mips32&MIPS_MACHINE!=msim&MIPS_MACHINE!=simics] "fpu/mips1" Mips FPU test 1 |
@ "print/print1" Printf test 1 |
@ "thread/thread1" Thread test 1 |