/kernel/trunk/arch/amd64/include/mm/page.h |
---|
47,6 → 47,11 |
# define PA2KA(x) ((x) + 0xffffffff80000000) |
#endif |
#define PTL0_ENTRIES_ARCH 512 |
#define PTL1_ENTRIES_ARCH 512 |
#define PTL2_ENTRIES_ARCH 512 |
#define PTL3_ENTRIES_ARCH 512 |
#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>39)&0x1ff) |
#define PTL1_INDEX_ARCH(vaddr) (((vaddr)>>30)&0x1ff) |
#define PTL2_INDEX_ARCH(vaddr) (((vaddr)>>21)&0x1ff) |
73,6 → 78,8 |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) set_pt_flags((pte_t *)(ptl2), (index_t)(i), (x)) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) |
#define PTE_VALID_ARCH(p) (*((__u64 *) (p)) != 0) |
#ifndef __ASM__ |
/** Page Table Entry. */ |
/kernel/trunk/arch/mips32/include/mm/page.h |
---|
58,6 → 58,11 |
* - PTL3 has 4096 entries (12 bits) |
*/ |
#define PTL0_ENTRIES_ARCH 64 |
#define PTL1_ENTRIES_ARCH 0 |
#define PTL2_ENTRIES_ARCH 0 |
#define PTL3_ENTRIES_ARCH 4096 |
#define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26) |
#define PTL1_INDEX_ARCH(vaddr) 0 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
85,6 → 90,8 |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) |
#define PTE_VALID_ARCH(p) (*((__u32 *) (p)) != 0) |
#ifndef __ASM__ |
#include <arch/mm/tlb.h> |
/kernel/trunk/arch/ia32/include/mm/page.h |
---|
44,6 → 44,11 |
* Implementation of generic 4-level page table interface. |
* IA-32 has 2-level page tables, so PTL1 and PTL2 are left out. |
*/ |
#define PTL0_ENTRIES_ARCH 1024 |
#define PTL1_ENTRIES_ARCH 0 |
#define PTL2_ENTRIES_ARCH 0 |
#define PTL3_ENTRIES_ARCH 1024 |
#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>22)&0x3ff) |
#define PTL1_INDEX_ARCH(vaddr) 0 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
70,6 → 75,8 |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) |
#define PTE_VALID_ARCH(p) (*((__u32 *) (p)) != 0) |
#ifndef __ASM__ |
#include <mm/page.h> |