/kernel/trunk/arch/mips32/src/exception.c |
---|
95,7 → 95,7 |
static void reserved_instr_exception(int n, istate_t *istate) |
{ |
if (*((__u32 *)istate->epc) == 0x7c03e83b) { |
if (*((uint32_t *)istate->epc) == 0x7c03e83b) { |
ASSERT(THREAD); |
istate->epc += 4; |
istate->v1 = istate->k1; |
139,7 → 139,7 |
static void interrupt_exception(int n, istate_t *istate) |
{ |
__u32 cause; |
uint32_t cause; |
int i; |
/* decode interrupt number and process the interrupt */ |
/kernel/trunk/arch/mips32/src/mips32.c |
---|
71,7 → 71,7 |
/* Why the linker moves the variable 64K away in assembler |
* when not in .text section ???????? |
*/ |
__address supervisor_sp __attribute__ ((section (".text"))); |
uintptr_t supervisor_sp __attribute__ ((section (".text"))); |
/* Stack pointer saved when entering user mode */ |
/* TODO: How do we do it on SMP system???? */ |
bootinfo_t bootinfo __attribute__ ((section (".text"))); |
81,7 → 81,7 |
/* Setup usermode */ |
init.cnt = bootinfo.cnt; |
__u32 i; |
uint32_t i; |
for (i = 0; i < bootinfo.cnt; i++) { |
init.tasks[i].addr = bootinfo.tasks[i].addr; |
146,10 → 146,10 |
cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
cp0_status_um_bit | |
cp0_status_ie_enabled_bit)); |
cp0_epc_write((__address) kernel_uarg->uspace_entry); |
userspace_asm(((__address) kernel_uarg->uspace_stack+PAGE_SIZE), |
(__address) kernel_uarg->uspace_uarg, |
(__address) kernel_uarg->uspace_entry); |
cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry); |
userspace_asm(((uintptr_t) kernel_uarg->uspace_stack+PAGE_SIZE), |
(uintptr_t) kernel_uarg->uspace_uarg, |
(uintptr_t) kernel_uarg->uspace_entry); |
while (1) |
; |
} |
162,7 → 162,7 |
/** Perform mips32 specific tasks needed before the new thread is scheduled. */ |
void before_thread_runs_arch(void) |
{ |
supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
} |
void after_thread_ran_arch(void) |
174,7 → 174,7 |
* We have it currently in K1, it is |
* possible to have it separately in the future. |
*/ |
__native sys_tls_set(__native addr) |
unative_t sys_tls_set(unative_t addr) |
{ |
return 0; |
} |
/kernel/trunk/arch/mips32/src/ddi/ddi.c |
---|
50,7 → 50,7 |
* |
* @return 0 on success or an error code from errno.h. |
*/ |
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size) |
int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) |
{ |
return 0; |
} |
/kernel/trunk/arch/mips32/src/debugger.c |
---|
91,8 → 91,8 |
}; |
static struct { |
__u32 andmask; |
__u32 value; |
uint32_t andmask; |
uint32_t value; |
}jmpinstr[] = { |
{0xf3ff0000, 0x41000000}, /* BCzF */ |
{0xf3ff0000, 0x41020000}, /* BCzFL */ |
125,7 → 125,7 |
* @param instr Instruction code |
* @return true - it is jump instruction, false otherwise |
*/ |
static bool is_jump(__native instr) |
static bool is_jump(unative_t instr) |
{ |
int i; |
153,12 → 153,12 |
/* Check, that the breakpoints do not conflict */ |
for (i=0; i<BKPOINTS_MAX; i++) { |
if (breakpoints[i].address == (__address)argv->intval) { |
if (breakpoints[i].address == (uintptr_t)argv->intval) { |
printf("Duplicate breakpoint %d.\n", i); |
spinlock_unlock(&bkpoints_lock); |
return 0; |
} else if (breakpoints[i].address == (__address)argv->intval + sizeof(__native) || \ |
breakpoints[i].address == (__address)argv->intval - sizeof(__native)) { |
} else if (breakpoints[i].address == (uintptr_t)argv->intval + sizeof(unative_t) || \ |
breakpoints[i].address == (uintptr_t)argv->intval - sizeof(unative_t)) { |
printf("Adjacent breakpoints not supported, conflict with %d.\n", i); |
spinlock_unlock(&bkpoints_lock); |
return 0; |
177,10 → 177,10 |
interrupts_restore(ipl); |
return 0; |
} |
cur->address = (__address) argv->intval; |
cur->address = (uintptr_t) argv->intval; |
printf("Adding breakpoint on address: %p\n", argv->intval); |
cur->instruction = ((__native *)cur->address)[0]; |
cur->nextinstruction = ((__native *)cur->address)[1]; |
cur->instruction = ((unative_t *)cur->address)[0]; |
cur->nextinstruction = ((unative_t *)cur->address)[1]; |
if (argv == &add_argv) { |
cur->flags = 0; |
} else { /* We are add extended */ |
192,7 → 192,7 |
cur->counter = 0; |
/* Set breakpoint */ |
*((__native *)cur->address) = 0x0d; |
*((unative_t *)cur->address) = 0x0d; |
spinlock_unlock(&bkpoint_lock); |
interrupts_restore(ipl); |
228,8 → 228,8 |
interrupts_restore(ipl); |
return 0; |
} |
((__u32 *)cur->address)[0] = cur->instruction; |
((__u32 *)cur->address)[1] = cur->nextinstruction; |
((uint32_t *)cur->address)[0] = cur->instruction; |
((uint32_t *)cur->address)[1] = cur->nextinstruction; |
cur->address = NULL; |
298,7 → 298,7 |
void debugger_bpoint(istate_t *istate) |
{ |
bpinfo_t *cur = NULL; |
__address fireaddr = istate->epc; |
uintptr_t fireaddr = istate->epc; |
int i; |
/* test branch delay slot */ |
315,7 → 315,7 |
} |
/* Reinst only breakpoint */ |
if ((breakpoints[i].flags & BKPOINT_REINST) \ |
&& (fireaddr ==breakpoints[i].address+sizeof(__native))) { |
&& (fireaddr ==breakpoints[i].address+sizeof(unative_t))) { |
cur = &breakpoints[i]; |
break; |
} |
323,9 → 323,9 |
if (cur) { |
if (cur->flags & BKPOINT_REINST) { |
/* Set breakpoint on first instruction */ |
((__u32 *)cur->address)[0] = 0x0d; |
((uint32_t *)cur->address)[0] = 0x0d; |
/* Return back the second */ |
((__u32 *)cur->address)[1] = cur->nextinstruction; |
((uint32_t *)cur->address)[1] = cur->nextinstruction; |
cur->flags &= ~BKPOINT_REINST; |
spinlock_unlock(&bkpoint_lock); |
return; |
338,11 → 338,11 |
fireaddr, get_symtab_entry(istate->epc)); |
/* Return first instruction back */ |
((__u32 *)cur->address)[0] = cur->instruction; |
((uint32_t *)cur->address)[0] = cur->instruction; |
if (! (cur->flags & BKPOINT_ONESHOT)) { |
/* Set Breakpoint on next instruction */ |
((__u32 *)cur->address)[1] = 0x0d; |
((uint32_t *)cur->address)[1] = 0x0d; |
cur->flags |= BKPOINT_REINST; |
} |
cur->flags |= BKPOINT_INPROG; |
/kernel/trunk/arch/mips32/src/mm/tlb.c |
---|
51,10 → 51,10 |
static void tlb_invalid_fail(istate_t *istate); |
static void tlb_modified_fail(istate_t *istate); |
static pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc); |
static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc); |
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn); |
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr); |
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn); |
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr); |
/** Initialize TLB |
* |
96,7 → 96,7 |
entry_lo_t lo; |
entry_hi_t hi; |
asid_t asid; |
__address badvaddr; |
uintptr_t badvaddr; |
pte_t *pte; |
int pfrc; |
166,7 → 166,7 |
void tlb_invalid(istate_t *istate) |
{ |
tlb_index_t index; |
__address badvaddr; |
uintptr_t badvaddr; |
entry_lo_t lo; |
entry_hi_t hi; |
pte_t *pte; |
250,7 → 250,7 |
void tlb_modified(istate_t *istate) |
{ |
tlb_index_t index; |
__address badvaddr; |
uintptr_t badvaddr; |
entry_lo_t lo; |
entry_hi_t hi; |
pte_t *pte; |
383,7 → 383,7 |
* |
* @return PTE on success, NULL otherwise. |
*/ |
pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc) |
pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc) |
{ |
entry_hi_t hi; |
pte_t *pte; |
445,7 → 445,7 |
} |
} |
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn) |
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn) |
{ |
lo->value = 0; |
lo->g = g; |
455,7 → 455,7 |
lo->pfn = pfn; |
} |
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr) |
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr) |
{ |
hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); |
hi->asid = asid; |
567,7 → 567,7 |
* @param page First page whose TLB entry is to be invalidated. |
* @param cnt Number of entries to invalidate. |
*/ |
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
{ |
int i; |
ipl_t ipl; |
/kernel/trunk/arch/mips32/src/mm/page.c |
---|
45,7 → 45,7 |
* - on mips, all devices are already mapped into kernel space, |
* translate the physical address to uncached area |
*/ |
__address hw_map(__address physaddr, size_t size) |
uintptr_t hw_map(uintptr_t physaddr, size_t size) |
{ |
return physaddr + 0xa0000000; |
} |
/kernel/trunk/arch/mips32/src/interrupt.c |
---|
132,7 → 132,7 |
} |
/* Reregister irq to be IPC-ready */ |
void irq_ipc_bind_arch(__native irq) |
void irq_ipc_bind_arch(unative_t irq) |
{ |
/* Do not allow to redefine timer */ |
/* Swint0, Swint1 are already handled */ |
/kernel/trunk/arch/mips32/src/drivers/arc.c |
---|
142,7 → 142,7 |
switch (configdata->descr[i].type) { |
case CmResourceTypePort: |
printf("Port: %p-size:%d ", |
(__address)configdata->descr[i].u.port.start, |
(uintptr_t)configdata->descr[i].u.port.start, |
configdata->descr[i].u.port.length); |
break; |
case CmResourceTypeInterrupt: |
152,7 → 152,7 |
break; |
case CmResourceTypeMemory: |
printf("Memory: %p-size:%d ", |
(__address)configdata->descr[i].u.port.start, |
(uintptr_t)configdata->descr[i].u.port.start, |
configdata->descr[i].u.port.length); |
break; |
default: |
236,7 → 236,7 |
/** Print charactor to console */ |
static void arc_putchar(char ch) |
{ |
__u32 cnt; |
uint32_t cnt; |
ipl_t ipl; |
/* TODO: Should be spinlock? */ |
293,7 → 293,7 |
static void arc_keyboard_poll(void) |
{ |
char ch; |
__u32 count; |
uint32_t count; |
long result; |
if (! kbd_polling_enabled) |
316,7 → 316,7 |
static char arc_read(chardev_t *dev) |
{ |
char ch; |
__u32 count; |
uint32_t count; |
long result; |
result = arc_entry->read(0, &ch, 1, &count); |
380,7 → 380,7 |
{ |
arc_memdescriptor_t *desc; |
int total = 0; |
__address base; |
uintptr_t base; |
size_t basesize; |
desc = arc_entry->getmemorydescriptor(NULL); |