/kernel/trunk/arch/mips32/src/exception.c |
---|
48,7 → 48,10 |
#include <arch/debugger.h> |
static char * exctable[] = { |
"Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store", |
"Interrupt", |
"TLB Modified", |
"TLB Invalid", |
"TLB Invalid Store", |
"Address Error - load/instr. fetch", |
"Address Error - store", |
"Bus Error - fetch instruction", |
174,4 → 177,3 |
/** @} |
*/ |
/kernel/trunk/arch/mips32/src/cache.c |
---|
33,11 → 33,13 |
*/ |
#include <arch/cache.h> |
#include <arch/exception.h> |
#include <typedefs.h> |
#include <panic.h> |
void cache_error(void) |
void cache_error(istate_t *istate) |
{ |
panic("cache_error exception\n"); |
panic("cache_error exception (epc=%p)\n", istate->epc); |
} |
/** @} |
/kernel/trunk/arch/mips32/src/start.S |
---|
309,7 → 309,7 |
sw $sp,EOFFSET_SP($k0) |
add $sp, $k0, 0 |
jal tlb_refill /* tlb_refill(register_space) */ |
jal tlb_refill |
add $a0, $sp, 0 |
REGISTERS_LOAD $sp |
324,7 → 324,7 |
add $sp, $k0, 0 |
jal cache_error |
nop |
add $a0, $sp, 0 |
REGISTERS_LOAD $sp |