/kernel/trunk/arch/mips32/include/mm/asid.h |
---|
0,0 → 1,39 |
/* |
* Copyright (C) 2005 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_ASID_H__ |
#define __mips32_ASID_H__ |
#include <arch/types.h> |
#define ASID_STEALING_ENABLED 1 |
#define ASID_MAX_ARCH 255 |
typedef __u8 asid_t; |
#endif |
/kernel/trunk/arch/mips32/include/mm/as.h |
---|
0,0 → 1,44 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_AS_H__ |
#define __mips32_AS_H__ |
#include <arch/types.h> |
#include <typedefs.h> |
#define KERNEL_ADDRESS_SPACE_START_ARCH (__address) 0x80000000 |
#define KERNEL_ADDRESS_SPACE_END_ARCH (__address) 0xffffffff |
#define USER_ADDRESS_SPACE_START_ARCH (__address) 0x00000000 |
#define USER_ADDRESS_SPACE_END_ARCH (__address) 0x7fffffff |
#define UTEXT_ADDRESS_ARCH 0x00004000 |
#define USTACK_ADDRESS_ARCH (0x80000000-PAGE_SIZE) |
#define UDATA_ADDRESS_ARCH 0x01001000 |
#endif |
/kernel/trunk/arch/mips32/include/mm/tlb.h |
---|
0,0 → 1,145 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_TLB_H__ |
#define __mips32_TLB_H__ |
#include <arch/exception.h> |
#include <typedefs.h> |
#ifdef TLBCNT |
# define TLB_ENTRY_COUNT TLBCNT |
#else |
# define TLB_ENTRY_COUNT 48 |
#endif |
#define TLB_WIRED 1 |
#define TLB_KSTACK_WIRED_INDEX 0 |
#define TLB_PAGE_MASK_16K (0x3<<13) |
#define PAGE_UNCACHED 2 |
#define PAGE_CACHEABLE_EXC_WRITE 5 |
typedef union entry_lo entry_lo_t; |
typedef union entry_hi entry_hi_t; |
typedef union page_mask page_mask_t; |
typedef union index tlb_index_t; |
union entry_lo { |
struct { |
unsigned g : 1; /* global bit */ |
unsigned v : 1; /* valid bit */ |
unsigned d : 1; /* dirty/write-protect bit */ |
unsigned c : 3; /* cache coherency attribute */ |
unsigned pfn : 24; /* frame number */ |
unsigned : 2; /* zero */ |
} __attribute__ ((packed)); |
__u32 value; |
}; |
union pte { |
entry_lo_t lo; |
struct { |
unsigned : 30; |
unsigned w : 1; /* writable */ |
unsigned a : 1; /* accessed */ |
} __attribute__ ((packed)); |
}; |
union entry_hi { |
struct { |
unsigned asid : 8; |
unsigned : 5; |
unsigned vpn2 : 19; |
} __attribute__ ((packed)); |
__u32 value; |
}; |
union page_mask { |
struct { |
unsigned : 13; |
unsigned mask : 12; |
unsigned : 7; |
} __attribute__ ((packed)); |
__u32 value; |
}; |
union index { |
struct { |
unsigned index : 4; |
unsigned : 27; |
unsigned p : 1; |
} __attribute__ ((packed)); |
__u32 value; |
}; |
/** Probe TLB for Matching Entry |
* |
* Probe TLB for Matching Entry. |
*/ |
static inline void tlbp(void) |
{ |
__asm__ volatile ("tlbp\n\t"); |
} |
/** Read Indexed TLB Entry |
* |
* Read Indexed TLB Entry. |
*/ |
static inline void tlbr(void) |
{ |
__asm__ volatile ("tlbr\n\t"); |
} |
/** Write Indexed TLB Entry |
* |
* Write Indexed TLB Entry. |
*/ |
static inline void tlbwi(void) |
{ |
__asm__ volatile ("tlbwi\n\t"); |
} |
/** Write Random TLB Entry |
* |
* Write Random TLB Entry. |
*/ |
static inline void tlbwr(void) |
{ |
__asm__ volatile ("tlbwr\n\t"); |
} |
#define tlb_invalidate(asid) tlb_invalidate_asid(asid) |
extern void tlb_invalid(struct exception_regdump *pstate); |
extern void tlb_refill(struct exception_regdump *pstate); |
extern void tlb_modified(struct exception_regdump *pstate); |
#endif |
/kernel/trunk/arch/mips32/include/mm/memory_init.h |
---|
0,0 → 1,39 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_MEMORY_INIT_H__ |
#define __mips32_MEMORY_INIT_H__ |
#include <config.h> |
/* When this function is called, we do not have ARC initiated |
* - provide some reasonable minimum and update it later |
*/ |
#define get_memory_size() CONFIG_MEMORY_SIZE |
#endif |
/kernel/trunk/arch/mips32/include/mm/page.h |
---|
0,0 → 1,122 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_PAGE_H__ |
#define __mips32_PAGE_H__ |
#define PAGE_SIZE FRAME_SIZE |
#ifndef __ASM__ |
# define KA2PA(x) (((__address) (x)) - 0x80000000) |
# define PA2KA(x) (((__address) (x)) + 0x80000000) |
#else |
# define KA2PA(x) ((x) - 0x80000000) |
# define PA2KA(x) ((x) + 0x80000000) |
#endif |
/* |
* Implementation of generic 4-level page table interface. |
* NOTE: this implementation is under construction |
* |
* Page table layout: |
* - 32-bit virtual addresses |
* - Offset is 14 bits => pages are 16K long |
* - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long |
* - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed) |
* - PTL0 has 64 entries (6 bits) |
* - PTL1 is not used |
* - PTL2 is not used |
* - PTL3 has 4096 entries (12 bits) |
*/ |
#define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26) |
#define PTL1_INDEX_ARCH(vaddr) 0 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>14)&0x3fff) |
#define GET_PTL0_ADDRESS_ARCH() (PTL0) |
#define SET_PTL0_ADDRESS_ARCH(ptl0) (PTL0 = (pte_t *)(ptl0)) |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].lo.pfn<<12) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].lo.pfn<<12) |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].lo.pfn = (a)>>12) |
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].lo.pfn = (a)>>12) |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i)) |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) |
#ifndef __ASM__ |
#include <arch/mm/tlb.h> |
#include <mm/page.h> |
#include <arch/mm/frame.h> |
#include <arch/types.h> |
static inline int get_pt_flags(pte_t *pt, index_t i) |
{ |
pte_t *p = &pt[i]; |
return ( |
((p->lo.c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) | |
((!p->lo.v)<<PAGE_PRESENT_SHIFT) | |
(1<<PAGE_USER_SHIFT) | |
(1<<PAGE_READ_SHIFT) | |
((p->w)<<PAGE_WRITE_SHIFT) | |
(1<<PAGE_EXEC_SHIFT) |
); |
} |
static inline void set_pt_flags(pte_t *pt, index_t i, int flags) |
{ |
pte_t *p = &pt[i]; |
p->lo.c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
p->lo.v = !(flags & PAGE_NOT_PRESENT); |
p->w = (flags & PAGE_WRITE) != 0; |
} |
extern void page_arch_init(void); |
extern pte_t *PTL0; |
#endif /* __ASM__ */ |
#endif |
/kernel/trunk/arch/mips32/include/mm/frame.h |
---|
0,0 → 1,36 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_FRAME_H__ |
#define __mips32_FRAME_H__ |
#define FRAME_SIZE 16384 |
extern void frame_arch_init(void); |
#endif |
/kernel/trunk/arch/mips32/include/memstr.h |
---|
0,0 → 1,39 |
/* |
* Copyright (C) 2005 Sergey Bondari |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_MEMSTR_H__ |
#define __mips32_MEMSTR_H__ |
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
extern void memsetw(__address dst, size_t cnt, __u16 x); |
extern void memsetb(__address dst, size_t cnt, __u8 x); |
extern int memcmp(__address src, __address dst, int cnt); |
#endif |
/kernel/trunk/arch/mips32/include/debugger.h |
---|
0,0 → 1,60 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef _mips32_DEBUGGER_H_ |
#define _mips32_DEBUGGER_H_ |
#include <typedefs.h> |
#include <arch/exception.h> |
#include <arch/types.h> |
#define BKPOINTS_MAX 10 |
#define BKPOINT_INPROG (1 << 0) /**< Breakpoint was shot */ |
#define BKPOINT_ONESHOT (1 << 1) /**< One-time breakpoint,mandatory for j/b |
instructions */ |
#define BKPOINT_REINST (1 << 2) /**< Breakpoint is set on the next |
instruction, so that it could be |
reinstalled on the previous one */ |
#define BKPOINT_FUNCCALL (1 << 3) /**< Call a predefined function */ |
typedef struct { |
__address address; /**< Breakpoint address */ |
__native instruction; /**< Original instruction */ |
__native nextinstruction; /**< Original instruction following break */ |
int flags; /**< Flags regarding breakpoint */ |
count_t counter; |
void (*bkfunc)(void *b, struct exception_regdump *pstate); |
} bpinfo_t; |
extern void debugger_init(void); |
void debugger_bpoint(struct exception_regdump *pstate); |
extern bpinfo_t breakpoints[BKPOINTS_MAX]; |
#endif |
/kernel/trunk/arch/mips32/include/atomic.h |
---|
0,0 → 1,84 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_ATOMIC_H__ |
#define __mips32_ATOMIC_H__ |
#include <arch/types.h> |
#define atomic_inc(x) ((void) atomic_add(x, 1)) |
#define atomic_dec(x) ((void) atomic_add(x, -1)) |
#define atomic_inc_pre(x) (atomic_add(x, 1) - 1) |
#define atomic_dec_pre(x) (atomic_add(x, -1) + 1) |
#define atomic_inc_post(x) atomic_add(x, 1) |
#define atomic_dec_post(x) atomic_add(x, -1) |
typedef struct { volatile __u32 count; } atomic_t; |
/* Atomic addition of immediate value. |
* |
* @param val Memory location to which will be the immediate value added. |
* @param i Signed immediate that will be added to *val. |
* |
* @return Value after addition. |
*/ |
static inline count_t atomic_add(atomic_t *val, int i) |
{ |
count_t tmp, v; |
__asm__ volatile ( |
"1:\n" |
" ll %0, %1\n" |
" addiu %0, %0, %3\n" /* same as addi, but never traps on overflow */ |
" move %2, %0\n" |
" sc %0, %1\n" |
" beq %0, %4, 1b\n" /* if the atomic operation failed, try again */ |
/* nop */ /* nop is inserted automatically by compiler */ |
: "=r" (tmp), "=m" (val->count), "=r" (v) |
: "i" (i), "i" (0) |
); |
return v; |
} |
/* Reads/writes are atomic on mips for 4-bytes */ |
static inline void atomic_set(atomic_t *val, __u32 i) |
{ |
val->count = i; |
} |
static inline __u32 atomic_get(atomic_t *val) |
{ |
return val->count; |
} |
#endif |
/kernel/trunk/arch/mips32/include/debug.h |
---|
0,0 → 1,46 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_DEBUG_H__ |
#define __mips23_DEBUG_H__ |
/** simulator enters the trace mode */ |
#define ___traceon() asm volatile ( "\t.word\t0x39\n"); |
/** simulator leaves the trace mode */ |
#define ___traceoff() asm volatile ( "\t.word\t0x3d\n"); |
/** register dump */ |
#define ___regview() asm volatile ( "\t.word\t0x37\n"); |
/** halt the simulator */ |
#define ___halt() asm volatile ( "\t.word\t0x28\n"); |
/** simulator enters interactive mode */ |
#define ___intmode() asm volatile ( "\t.word\t0x29\n"); |
#endif |
/kernel/trunk/arch/mips32/include/cp0.h |
---|
0,0 → 1,103 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_CP0_H__ |
#define __mips32_CP0_H__ |
#include <arch/types.h> |
#include <arch/mm/tlb.h> |
#define cp0_status_ie_enabled_bit (1<<0) |
#define cp0_status_exl_exception_bit (1<<1) |
#define cp0_status_erl_error_bit (1<<2) |
#define cp0_status_um_bit (1<<4) |
#define cp0_status_bev_bootstrap_bit (1<<22) |
#define cp0_status_fpu_bit (1<<29) |
#define cp0_status_im_shift 8 |
#define cp0_status_im_mask 0xff00 |
#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) |
#define fpu_cop_id 1 |
/* |
* Magic value for use in msim. |
* On AMD Duron 800Mhz, this roughly seems like one us. |
*/ |
#define cp0_compare_value 10000 |
#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |
extern __u32 cp0_index_read(void); |
extern void cp0_index_write(__u32 val); |
extern __u32 cp0_random_read(void); |
extern __u32 cp0_entry_lo0_read(void); |
extern void cp0_entry_lo0_write(__u32 val); |
extern __u32 cp0_entry_lo1_read(void); |
extern void cp0_entry_lo1_write(__u32 val); |
extern __u32 cp0_context_read(void); |
extern void cp0_context_write(__u32 val); |
extern __u32 cp0_pagemask_read(void); |
extern void cp0_pagemask_write(__u32 val); |
extern __u32 cp0_wired_read(void); |
extern void cp0_wired_write(__u32 val); |
extern __u32 cp0_badvaddr_read(void); |
extern __u32 cp0_count_read(void); |
extern void cp0_count_write(__u32 val); |
extern __u32 cp0_entry_hi_read(void); |
extern void cp0_entry_hi_write(__u32 val); |
extern __u32 cp0_compare_read(void); |
extern void cp0_compare_write(__u32 val); |
extern __u32 cp0_status_read(void); |
extern void cp0_status_write(__u32 val); |
extern __u32 cp0_cause_read(void); |
extern void cp0_cause_write(__u32 val); |
extern __u32 cp0_epc_read(void); |
extern void cp0_epc_write(__u32 val); |
extern __u32 cp0_prid_read(void); |
#endif |
/kernel/trunk/arch/mips32/include/drivers/serial.h |
---|
0,0 → 1,62 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __DRV_SERIAL_H__ |
#define __DRV_SERIAL_H__ |
#include <console/chardev.h> |
#define SERIAL_MAX 4 |
#define SERIAL_COM1 0x3f8 |
#define SERIAL_COM1_IRQ 4 |
#define SERIAL_COM2 0x2f8 |
#define SERIAL_COM2_IRQ 3 |
#define P_WRITEB(where,what) (*((volatile char *) (0xB8000000+where))=what) |
#define P_READB(where) (*((volatile char *)(0xB8000000+where))) |
#define SERIAL_READ(x) P_READB(x) |
#define SERIAL_WRITE(x,c) P_WRITEB(x,c) |
/* Interrupt enable register */ |
#define SERIAL_READ_IER(x) (P_READB((x) + 1)) |
#define SERIAL_WRITE_IER(x,c) (P_WRITEB((x)+1,c)) |
/* Interrupt identification register */ |
#define SERIAL_READ_IIR(x) (P_READB((x) + 2)) |
/* Line status register */ |
#define SERIAL_READ_LSR(x) (P_READB((x) + 5)) |
#define TRANSMIT_EMPTY_BIT 5 |
typedef struct { |
int port; |
int irq; |
}serial_t; |
void serial_console(void); |
int serial_init(void); |
#endif |
/kernel/trunk/arch/mips32/include/drivers/arc.h |
---|
0,0 → 1,220 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_ARC_H__ |
#define __mips32_ARC_H__ |
#include <arch/types.h> |
#include <console/chardev.h> |
#define ARC_BASE_ADDR 0x1000; |
#define ARC_MAGIC 0x53435241 |
/* Frame size used by ARC */ |
#define ARC_FRAME 4096 |
typedef enum { |
SystemClass = 0, |
ProcessorClass, |
CacheClass, |
AdapterClass, |
ControllerClass, |
PeripheralClass, |
MemoryClass |
} arc_component_class; |
typedef enum { |
ARC_type = 0, |
CPU_type, |
FPU_type, |
PrimaryICache, |
PrimaryDCache, |
SecondaryICache, |
SecondaryDCache, |
SecondaryCache, |
Memory, /* Not in NT PROM */ |
EISAAdapter, |
TCAdapter, |
SCSIAdapter, |
DTIAdapter, |
MultiFunctionAdapter, |
DiskController, |
TapeController, |
CDROMController, |
WORMController, |
SerialController, |
NetworkController, |
DisplayController, |
ParallelController, |
PointerController, |
KeyboardController, |
AudioController, |
OtherController, |
DiskPeripheral, |
FloppyDiskPeripheral, |
TapePeripheral, |
ModemPeripheral, |
MonitorPeripheral, |
PrinterPeripheral, |
PointerPeripheral, |
KeyboardPeripheral, |
TerminalPeripheral, |
LinePeripheral, |
NetworkPeripheral, |
OtherPeripheral, |
XTalkAdapter, |
PCIAdapter, |
GIOAdapter, |
TPUAdapter, |
Anonymous |
}arc_component_type; |
typedef enum { |
Failed = 1, |
ReadOnly = 2, |
Removable = 4, |
ConsoleIn = 8, |
ConsoleOut = 16, |
Input = 32, |
Output = 64 |
}arc_component_flags; |
typedef struct { |
arc_component_class class; |
arc_component_type type; |
arc_component_flags flags; |
__u16 revision; |
__u16 version; |
__u32 key; |
__u32 affinitymask; |
__u32 configdatasize; |
__u32 identifier_len; |
char *identifier; |
} __attribute__ ((packed)) arc_component; |
typedef struct { |
__u16 year; |
__u16 month; |
__u16 day; |
__u16 hour; |
__u16 minutes; |
__u16 seconds; |
__u16 mseconds; |
} __attribute__ ((packed)) arc_timeinfo; |
/* This is the SGI block structure, WinNT has it different */ |
typedef enum { |
ExceptionBlock, |
SystemParameterBlock, |
FreeContiguous, |
FreeMemory, |
BadMemory, |
LoadedProgram, |
FirmwareTemporary, |
FirmwarePermanent |
}arc_memorytype_t; |
typedef struct { |
arc_memorytype_t type; |
__u32 basepage; /* *4096 = baseaddr */ |
__u32 basecount; |
}arc_memdescriptor_t; |
typedef struct { |
char vendorid[8]; |
char prodid[8]; |
}arc_sysid_t; |
typedef struct { |
long (*load)(void); /* ... */ |
long (*invoke)(__u32 eaddr,__u32 saddr,__u32 argc,char **argv, |
char **envp); |
long (*execute)(char *path,__u32 argc,char **argv,char **envp); |
void (*halt)(void); |
void (*powerdown)(void); |
void (*restart)(void); |
void (*reboot)(void); |
void (*enterinteractivemode)(void); |
long (*reserved)(void); |
/* 10 */ |
arc_component * (*getpeer)(arc_component *c); |
arc_component * (*getchild)(arc_component *c); |
arc_component * (*getparent)(arc_component *c); |
long (*getconfigurationdata)(void *configdata, arc_component *c); |
long (*addchild)(arc_component *c, arc_component *template, |
void *configdata); |
long (*deletecomponet)(arc_component *current); |
long (*getcomponent)(char *path); |
long (*saveconfiguration)(void); |
arc_sysid_t (*getsystemid)(void); |
arc_memdescriptor_t * (*getmemorydescriptor)(arc_memdescriptor_t *cur); |
/* 20 */ |
long (*reserved2)(void); |
arc_timeinfo * (*gettime)(void); |
__u32 (*getrelativetime)(void); |
long (*getdirectoryentry)(); |
long (*open)(void); /* ... */ |
long (*close)(__u32 fileid); |
long (*read)(__u32 fileid,void *buf,__u32 n,__u32 *cnt); |
long (*getreadstatus)(__u32 fileid); |
long (*write)(__u32 fileid, void *buf,__u32 n,__u32 *cnt); |
long (*seek)(void); /* ... */ |
/* 30 */ |
long (*mount)(void); /* ... */ |
char * (*getenvironmentvariable)(char *name); |
char * (*setenvironmentvariable)(char *name, char *value); |
long (*getfileinformation)(void); /* ... */ |
long (*setfileinformation)(__u32 fileid,__u32 attflags,__u32 attmask); |
void (*flushallcaches)(void); |
long (*testunicodecharacter)(void); /* ... */ |
long (*getdisplaystatus)(void); /* ... */ |
} arc_func_vector_t; |
typedef struct { |
__u32 signature; |
__u32 length; |
__u16 version; |
__u16 revision; |
void *restartblock; |
void *debugblock; |
void *gevector; |
void *utlbmissvector; |
__u32 firmwarevectorlen; |
arc_func_vector_t *firmwarevector; |
__u32 privvectorlen; |
void *privvector; |
__u32 adaptercount; |
}__attribute__ ((packed)) arc_sbp; |
extern int arc_init(void); |
extern void arc_print_memory_map(void); |
extern int arc_enabled(void); |
extern void arc_print_devices(void); |
void arc_frame_init(void); |
void arc_console(void); |
#endif |
/kernel/trunk/arch/mips32/include/drivers/msim.h |
---|
0,0 → 1,41 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef _MSIM_H_ |
#define _MSIM_H_ |
#include <console/chardev.h> |
#define MSIM_VIDEORAM 0xB0000000 |
/** Address of 'keyboard' device. */ |
#define MSIM_KBD_ADDRESS 0xB0000000 |
#define MSIM_KBD_IRQ 2 |
void msim_console(void); |
#endif |
/kernel/trunk/arch/mips32/include/interrupt.h |
---|
0,0 → 1,47 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_INTERRUPT_H__ |
#define __mips32_INTERRUPT_H__ |
#include <arch/exception.h> |
#define IVT_ITEMS 40 |
#define INT_OFFSET 32 |
#define int_register(it, name, handler) exc_register(((it)+INT_OFFSET),name,handler) |
#define IRQ2 2 |
#define IRQ3 3 |
#define IRQ7 7 |
#define TIMER_IRQ IRQ7 |
extern void interrupt_init(void); |
#endif |
/kernel/trunk/arch/mips32/include/exception.h |
---|
0,0 → 1,98 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_EXCEPTION_H__ |
#define __mips32_EXCEPTION_H__ |
#ifndef __mips32_TYPES_H__ |
# include <arch/types.h> |
#endif |
#define EXC_Int 0 |
#define EXC_Mod 1 |
#define EXC_TLBL 2 |
#define EXC_TLBS 3 |
#define EXC_AdEL 4 |
#define EXC_AdES 5 |
#define EXC_IBE 6 |
#define EXC_DBE 7 |
#define EXC_Sys 8 |
#define EXC_Bp 9 |
#define EXC_RI 10 |
#define EXC_CpU 11 |
#define EXC_Ov 12 |
#define EXC_Tr 13 |
#define EXC_VCEI 14 |
#define EXC_FPE 15 |
#define EXC_WATCH 23 |
#define EXC_VCED 31 |
struct exception_regdump { |
__u32 at; |
__u32 v0; |
__u32 v1; |
__u32 a0; |
__u32 a1; |
__u32 a2; |
__u32 a3; |
__u32 t0; |
__u32 t1; |
__u32 t2; |
__u32 t3; |
__u32 t4; |
__u32 t5; |
__u32 t6; |
__u32 t7; |
__u32 s0; |
__u32 s1; |
__u32 s2; |
__u32 s3; |
__u32 s4; |
__u32 s5; |
__u32 s6; |
__u32 s7; |
__u32 t8; |
__u32 t9; |
__u32 gp; |
__u32 sp; |
__u32 s8; |
__u32 ra; |
__u32 lo; |
__u32 hi; |
__u32 status; /* cp0_status */ |
__u32 epc; /* cp0_epc */ |
}; |
extern void exception(struct exception_regdump *pstate); |
extern void tlb_refill_entry(void); |
extern void exception_entry(void); |
extern void cache_error_entry(void); |
extern void exception_init(void); |
#endif |
/kernel/trunk/arch/mips32/include/console.h |
---|
0,0 → 1,35 |
/* |
* Copyright (C) 2005 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_CONSOLE_H__ |
#define __mips32_CONSOLE_H__ |
void console_init(void); |
#endif |
/kernel/trunk/arch/mips32/include/cpu.h |
---|
0,0 → 1,39 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_CPU_H__ |
#define __mips32_CPU_H__ |
#include <arch/types.h> |
struct cpu_arch { |
__u32 imp_num; |
__u32 rev_num; |
}; |
#endif |
/kernel/trunk/arch/mips32/include/context_offset.h |
---|
0,0 → 1,51 |
/* This file is automatically generated by gencontext.c. */ |
/* struct context */ |
#define OFFSET_SP 0x0 |
#define OFFSET_PC 0x4 |
#define OFFSET_S0 0x8 |
#define OFFSET_S1 0xc |
#define OFFSET_S2 0x10 |
#define OFFSET_S3 0x14 |
#define OFFSET_S4 0x18 |
#define OFFSET_S5 0x1c |
#define OFFSET_S6 0x20 |
#define OFFSET_S7 0x24 |
#define OFFSET_S8 0x28 |
#define OFFSET_GP 0x2c |
/* struct register_dump */ |
#define EOFFSET_AT 0x0 |
#define EOFFSET_V0 0x4 |
#define EOFFSET_V1 0x8 |
#define EOFFSET_A0 0xc |
#define EOFFSET_A1 0x10 |
#define EOFFSET_A2 0x14 |
#define EOFFSET_A3 0x18 |
#define EOFFSET_T0 0x1c |
#define EOFFSET_T1 0x20 |
#define EOFFSET_T2 0x24 |
#define EOFFSET_T3 0x28 |
#define EOFFSET_T4 0x2c |
#define EOFFSET_T5 0x30 |
#define EOFFSET_T6 0x34 |
#define EOFFSET_T7 0x38 |
#define EOFFSET_S0 0x3c |
#define EOFFSET_S1 0x40 |
#define EOFFSET_S2 0x44 |
#define EOFFSET_S3 0x48 |
#define EOFFSET_S4 0x4c |
#define EOFFSET_S5 0x50 |
#define EOFFSET_S6 0x54 |
#define EOFFSET_S7 0x58 |
#define EOFFSET_T8 0x5c |
#define EOFFSET_T9 0x60 |
#define EOFFSET_GP 0x64 |
#define EOFFSET_SP 0x68 |
#define EOFFSET_S8 0x6c |
#define EOFFSET_RA 0x70 |
#define EOFFSET_LO 0x74 |
#define EOFFSET_HI 0x78 |
#define EOFFSET_STATUS 0x7c |
#define EOFFSET_EPC 0x80 |
#define REGISTER_SPACE 132 |
/kernel/trunk/arch/mips32/include/arg.h |
---|
0,0 → 1,54 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_ARG_H__ |
#define __mips32_ARG_H__ |
#include <arch/types.h> |
typedef struct va_list { |
int pos; |
__u8 *last; |
} va_list; |
#define va_start(ap, lst) \ |
(ap).pos = sizeof(lst); \ |
(ap).last = (__u8 *) &(lst) |
/** |
* va_arg macro for MIPS32 - problem is that 64 bit values must be aligned on an 8-byte boundary (32bit values not) |
* To satisfy this, paddings must be sometimes inserted. |
*/ |
#define va_arg(ap, type) \ |
(*((type *)((ap).last + ((ap).pos += sizeof(type) + ((sizeof(type)==8)&&(((ap).pos)&(4))?4:0)) - sizeof(type)))) |
#define va_end(ap) |
#endif |
/kernel/trunk/arch/mips32/include/context.h |
---|
0,0 → 1,70 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_CONTEXT_H__ |
#define __mips32_CONTEXT_H__ |
#define STACK_ITEM_SIZE 4 |
/* |
* Put one item onto the stack to support get_stack_base(). |
*/ |
#define SP_DELTA (0+STACK_ITEM_SIZE) |
#ifndef __ASM__ |
#ifndef __mips32_TYPES_H__ |
# include <arch/types.h> |
#endif |
/* |
* Only save registers that must be preserved across |
* function calls. |
*/ |
struct context { |
__address sp; |
__address pc; |
__u32 s0; |
__u32 s1; |
__u32 s2; |
__u32 s3; |
__u32 s4; |
__u32 s5; |
__u32 s6; |
__u32 s7; |
__u32 s8; |
__u32 gp; |
ipl_t ipl; |
}; |
#endif /* __ASM__ */ |
#endif |
/kernel/trunk/arch/mips32/include/types.h |
---|
0,0 → 1,54 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_TYPES_H__ |
#define __mips32_TYPES_H__ |
#define NULL 0 |
typedef signed char __s8; |
typedef unsigned char __u8; |
typedef signed short __s16; |
typedef unsigned short __u16; |
typedef unsigned long __u32; |
typedef signed long __s32; |
typedef unsigned long long __u64; |
typedef signed long long __s64; |
typedef __u32 __address; |
typedef __u32 ipl_t; |
typedef __u32 __native; |
typedef union pte pte_t; |
#endif |
/kernel/trunk/arch/mips32/include/byteorder.h |
---|
0,0 → 1,51 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_BYTEORDER_H__ |
#define __mips32_BYTEORDER_H__ |
#include <arch/types.h> |
#include <byteorder.h> |
#ifdef BIG_ENDIAN |
static inline __u64 __u64_le2host(__u64 n) |
{ |
return __u64_byteorder_swap(n); |
} |
static inline __native __native_le2host(__native n) |
{ |
return __u32_byteorder_swap(n); |
} |
#else |
# define __native_le2host(n) (n) |
# define __u64_le2host(n) (n) |
#endif |
#endif |
/kernel/trunk/arch/mips32/include/asm/regname.h |
---|
0,0 → 1,89 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_REGNAME_H_ |
#define __mips32_REGNAME_H_ |
#define zero 0 |
#define at 1 |
#define v0 2 |
#define v1 3 |
#define a0 4 |
#define a1 5 |
#define a2 6 |
#define a3 7 |
#define t0 8 |
#define t1 9 |
#define t2 10 |
#define t3 11 |
#define t4 12 |
#define t5 13 |
#define t6 14 |
#define t7 15 |
#define s0 16 |
#define s1 17 |
#define s2 18 |
#define s3 19 |
#define s4 20 |
#define s5 21 |
#define s6 22 |
#define s7 23 |
#define t8 24 |
#define t9 25 |
#define k0 26 |
#define k1 27 |
#define gp 28 |
#define sp 29 |
#define s8 30 |
#define ra 31 |
#define index 0 |
#define random 1 |
#define entrylo0 2 |
#define entrylo1 3 |
#define context 4 |
#define pagemask 5 |
#define wired 6 |
#define badvaddr 8 |
#define count 9 |
#define entryhi 10 |
#define compare 11 |
#define status 12 |
#define cause 13 |
#define epc 14 |
#define config 16 |
#define lladdr 17 |
#define watchlo 18 |
#define watchhi 19 |
#define xcontext 20 |
#define debug 23 |
#define depc 24 |
#define eepc 30 |
#endif /* _REGNAME_H_ */ |
/kernel/trunk/arch/mips32/include/asm/boot.h |
---|
0,0 → 1,36 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_BOOT_H_ |
#define __mips32_BOOT_H_ |
/* Temporary stack size for boot process */ |
#define TEMP_STACK_SIZE 0x100 |
#endif |
/kernel/trunk/arch/mips32/include/fpu_context.h |
---|
0,0 → 1,39 |
/* |
* Copyright (C) 2005 Jakub Vana |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_FPU_CONTEXT_H__ |
#define __mips32_FPU_CONTEXT_H__ |
#include <arch/types.h> |
struct fpu_context { |
__native dregs[32]; |
__native cregs[32]; |
}; |
#endif |
/kernel/trunk/arch/mips32/include/cache.h |
---|
0,0 → 1,34 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_CACHE_H__ |
#define __mips32_CACHE_H__ |
extern void cache_error(void); |
#endif |
/kernel/trunk/arch/mips32/include/thread.h |
---|
0,0 → 1,36 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_THREAD_H__ |
#define __mips32_THREAD_H__ |
#include <arch/exception.h> |
#define ARCH_THREAD_DATA struct exception_regdump *pstate |
#endif |
/kernel/trunk/arch/mips32/include/arch.h |
---|
0,0 → 1,32 |
/* |
* Copyright (C) 2005 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_ARCH_H__ |
#define __mips32_ARCH_H__ |
#endif |
/kernel/trunk/arch/mips32/include/faddr.h |
---|
0,0 → 1,36 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_FADDR_H__ |
#define __mips32_FADDR_H__ |
#include <arch/types.h> |
#define FADDR(fptr) ((__address) (fptr)) |
#endif |
/kernel/trunk/arch/mips32/include/asm.h |
---|
0,0 → 1,62 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_ASM_H__ |
#define __mips32_ASM_H__ |
#include <arch/types.h> |
#include <typedefs.h> |
#include <config.h> |
static inline void cpu_sleep(void) |
{ |
/* Most of the simulators do not support */ |
/* __asm__ volatile ("wait"); */ |
} |
/** Return base address of current stack |
* |
* Return the base address of the current stack. |
* The stack is assumed to be STACK_SIZE bytes long. |
* The stack must start on page boundary. |
*/ |
static inline __address get_stack_base(void) |
{ |
__address v; |
__asm__ volatile ("and %0, $29, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
return v; |
} |
extern void cpu_halt(void); |
extern void asm_delay_loop(__u32 t); |
extern void userspace_asm(__address ustack); |
#endif |
/kernel/trunk/arch/mips32/include/barrier.h |
---|
0,0 → 1,42 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef __mips32_BARRIER_H__ |
#define __mips32_BARRIER_H__ |
/* |
* TODO: implement true MIPS memory barriers for macros below. |
*/ |
#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory") |
#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory") |
#define memory_barrier() |
#define read_barrier() |
#define write_barrier() |
#endif |
/kernel/trunk/arch/mips32/Makefile.inc |
---|
0,0 → 1,123 |
# |
# Copyright (C) 2005 Martin Decky |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions |
# are met: |
# |
# - Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# - Redistributions in binary form must reproduce the above copyright |
# notice, this list of conditions and the following disclaimer in the |
# documentation and/or other materials provided with the distribution. |
# - The name of the author may not be used to endorse or promote products |
# derived from this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
## Toolchain configuration |
# |
BFD_ARCH = mips |
TARGET = mipsel-linux-gnu |
TOOLCHAIN_DIR = /usr/local/mipsel/bin |
## Make some default assumptions |
# |
ifndef MIPS_MACHINE |
MIPS_MACHINE = msim |
endif |
KERNEL_LOAD_ADDRESS = 0x80100000 |
INIT_ADDRESS = 0x80110000 |
INIT_SIZE = 65536 |
CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss |
DEFS += -DMACHINE=${MIPS_MACHINE} -DKERNEL_LOAD_ADDRESS=${KERNEL_LOAD_ADDRESS} -DINIT_ADDRESS=${INIT_ADDRESS} -DINIT_SIZE=${INIT_SIZE} |
## Compile with hierarchical page tables support. |
# |
CONFIG_PAGE_PT = y |
## Compile with support for address space identifiers. |
# |
CONFIG_ASID = y |
CONFIG_ASID_FIFO = y |
## Accepted MACHINEs |
# |
ifeq ($(MIPS_MACHINE),indy) |
# GCC 4.0.1 compiled for mipsEL has problems compiling in |
# BigEndian mode with the swl/swr/lwl/lwr instructions. |
# We have to compile it with mips-sgi-irix5 to get it right. |
BFD_NAME = elf32-bigmips |
BFD = ecoff-bigmips --impure |
TARGET = mips-sgi-irix5 |
TOOLCHAIN_DIR = /usr/local/mips/bin |
KERNEL_LOAD_ADDRESS = 0x88002000 |
CFLAGS += -EB -DBIG_ENDIAN -DHAVE_FPU -march=r4600 |
endif |
ifeq ($(MIPS_MACHINE),lgxemul) |
BFD_NAME=elf32-tradlittlemips |
BFD = ecoff-littlemips |
CFLAGS += -DHAVE_FPU -mips3 |
endif |
ifeq ($(MIPS_MACHINE),bgxemul) |
BFD_NAME=elf32-bigmips |
BFD = ecoff-bigmips |
TARGET = mips-sgi-irix5 |
TOOLCHAIN_DIR = /usr/local/mips/bin |
CFLAGS += -EB -DBIG_ENDIAN -DHAVE_FPU -mips3 |
endif |
ifeq ($(MIPS_MACHINE),simics) |
# SIMICS 4kc emulation is broken, although for instructions |
# that do not bother us |
BFD_NAME = elf32-tradlittlemips |
BFD = elf32-tradlittlemips |
CFLAGS += -mhard-float -mips3 -DTLBCNT=16 |
TLBCNT = 16 |
endif |
ifeq ($(MIPS_MACHINE),msim) |
BFD_NAME = elf32-tradlittlemips |
BFD = binary |
CFLAGS += -mhard-float -mips3 |
endif |
ARCH_SOURCES = \ |
arch/$(ARCH)/src/start.S \ |
arch/$(ARCH)/src/context.S \ |
arch/$(ARCH)/src/panic.S \ |
arch/$(ARCH)/src/mips32.c \ |
arch/$(ARCH)/src/dummy.S \ |
arch/$(ARCH)/src/console.c \ |
arch/$(ARCH)/src/asm.S \ |
arch/$(ARCH)/src/exception.c \ |
arch/$(ARCH)/src/interrupt.c \ |
arch/$(ARCH)/src/cache.c \ |
arch/$(ARCH)/src/debugger.c \ |
arch/$(ARCH)/src/cpu/cpu.c \ |
arch/$(ARCH)/src/mm/frame.c \ |
arch/$(ARCH)/src/mm/page.c \ |
arch/$(ARCH)/src/mm/tlb.c \ |
arch/$(ARCH)/src/mm/as.c \ |
arch/$(ARCH)/src/fpu_context.c \ |
arch/$(ARCH)/src/drivers/arc.c \ |
arch/$(ARCH)/src/drivers/msim.c \ |
arch/$(ARCH)/src/drivers/serial.c |
/kernel/trunk/arch/mips32/src/mm/tlb.c |
---|
0,0 → 1,546 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch/mm/tlb.h> |
#include <mm/asid.h> |
#include <genarch/mm/asid_fifo.h> |
#include <mm/tlb.h> |
#include <mm/page.h> |
#include <mm/as.h> |
#include <arch/cp0.h> |
#include <panic.h> |
#include <arch.h> |
#include <symtab.h> |
#include <synch/spinlock.h> |
#include <print.h> |
#include <debug.h> |
static void tlb_refill_fail(struct exception_regdump *pstate); |
static void tlb_invalid_fail(struct exception_regdump *pstate); |
static void tlb_modified_fail(struct exception_regdump *pstate); |
static pte_t *find_mapping_and_check(__address badvaddr); |
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn); |
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr); |
/** Initialize TLB |
* |
* Initialize TLB. |
* Invalidate all entries and mark wired entries. |
*/ |
void tlb_arch_init(void) |
{ |
int i; |
asid_fifo_init(); |
cp0_pagemask_write(TLB_PAGE_MASK_16K); |
cp0_entry_hi_write(0); |
cp0_entry_lo0_write(0); |
cp0_entry_lo1_write(0); |
/* Clear and initialize TLB. */ |
for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
cp0_index_write(i); |
tlbwi(); |
} |
/* |
* The kernel is going to make use of some wired |
* entries (e.g. mapping kernel stacks in kseg3). |
*/ |
cp0_wired_write(TLB_WIRED); |
} |
/** Process TLB Refill Exception |
* |
* Process TLB Refill Exception. |
* |
* @param pstate Interrupted register context. |
*/ |
void tlb_refill(struct exception_regdump *pstate) |
{ |
entry_lo_t lo; |
entry_hi_t hi; |
__address badvaddr; |
pte_t *pte; |
badvaddr = cp0_badvaddr_read(); |
spinlock_lock(&AS->lock); |
pte = find_mapping_and_check(badvaddr); |
if (!pte) |
goto fail; |
/* |
* Record access to PTE. |
*/ |
pte->a = 1; |
prepare_entry_hi(&hi, AS->asid, badvaddr); |
prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn); |
/* |
* New entry is to be inserted into TLB |
*/ |
cp0_entry_hi_write(hi.value); |
if ((badvaddr/PAGE_SIZE) % 2 == 0) { |
cp0_entry_lo0_write(lo.value); |
cp0_entry_lo1_write(0); |
} |
else { |
cp0_entry_lo0_write(0); |
cp0_entry_lo1_write(lo.value); |
} |
cp0_pagemask_write(TLB_PAGE_MASK_16K); |
tlbwr(); |
spinlock_unlock(&AS->lock); |
return; |
fail: |
spinlock_unlock(&AS->lock); |
tlb_refill_fail(pstate); |
} |
/** Process TLB Invalid Exception |
* |
* Process TLB Invalid Exception. |
* |
* @param pstate Interrupted register context. |
*/ |
void tlb_invalid(struct exception_regdump *pstate) |
{ |
tlb_index_t index; |
__address badvaddr; |
entry_lo_t lo; |
entry_hi_t hi; |
pte_t *pte; |
badvaddr = cp0_badvaddr_read(); |
/* |
* Locate the faulting entry in TLB. |
*/ |
hi.value = cp0_entry_hi_read(); |
prepare_entry_hi(&hi, hi.asid, badvaddr); |
cp0_entry_hi_write(hi.value); |
tlbp(); |
index.value = cp0_index_read(); |
spinlock_lock(&AS->lock); |
/* |
* Fail if the entry is not in TLB. |
*/ |
if (index.p) { |
printf("TLB entry not found.\n"); |
goto fail; |
} |
pte = find_mapping_and_check(badvaddr); |
if (!pte) |
goto fail; |
/* |
* Read the faulting TLB entry. |
*/ |
tlbr(); |
/* |
* Record access to PTE. |
*/ |
pte->a = 1; |
prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn); |
/* |
* The entry is to be updated in TLB. |
*/ |
if ((badvaddr/PAGE_SIZE) % 2 == 0) |
cp0_entry_lo0_write(lo.value); |
else |
cp0_entry_lo1_write(lo.value); |
cp0_pagemask_write(TLB_PAGE_MASK_16K); |
tlbwi(); |
spinlock_unlock(&AS->lock); |
return; |
fail: |
spinlock_unlock(&AS->lock); |
tlb_invalid_fail(pstate); |
} |
/** Process TLB Modified Exception |
* |
* Process TLB Modified Exception. |
* |
* @param pstate Interrupted register context. |
*/ |
void tlb_modified(struct exception_regdump *pstate) |
{ |
tlb_index_t index; |
__address badvaddr; |
entry_lo_t lo; |
entry_hi_t hi; |
pte_t *pte; |
badvaddr = cp0_badvaddr_read(); |
/* |
* Locate the faulting entry in TLB. |
*/ |
hi.value = cp0_entry_hi_read(); |
prepare_entry_hi(&hi, hi.asid, badvaddr); |
cp0_entry_hi_write(hi.value); |
tlbp(); |
index.value = cp0_index_read(); |
spinlock_lock(&AS->lock); |
/* |
* Fail if the entry is not in TLB. |
*/ |
if (index.p) { |
printf("TLB entry not found.\n"); |
goto fail; |
} |
pte = find_mapping_and_check(badvaddr); |
if (!pte) |
goto fail; |
/* |
* Fail if the page is not writable. |
*/ |
if (!pte->w) |
goto fail; |
/* |
* Read the faulting TLB entry. |
*/ |
tlbr(); |
/* |
* Record access and write to PTE. |
*/ |
pte->a = 1; |
pte->lo.d = 1; |
prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn); |
/* |
* The entry is to be updated in TLB. |
*/ |
if ((badvaddr/PAGE_SIZE) % 2 == 0) |
cp0_entry_lo0_write(lo.value); |
else |
cp0_entry_lo1_write(lo.value); |
cp0_pagemask_write(TLB_PAGE_MASK_16K); |
tlbwi(); |
spinlock_unlock(&AS->lock); |
return; |
fail: |
spinlock_unlock(&AS->lock); |
tlb_modified_fail(pstate); |
} |
void tlb_refill_fail(struct exception_regdump *pstate) |
{ |
char *symbol = ""; |
char *sym2 = ""; |
char *s = get_symtab_entry(pstate->epc); |
if (s) |
symbol = s; |
s = get_symtab_entry(pstate->ra); |
if (s) |
sym2 = s; |
panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2); |
} |
void tlb_invalid_fail(struct exception_regdump *pstate) |
{ |
char *symbol = ""; |
char *s = get_symtab_entry(pstate->epc); |
if (s) |
symbol = s; |
panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol); |
} |
void tlb_modified_fail(struct exception_regdump *pstate) |
{ |
char *symbol = ""; |
char *s = get_symtab_entry(pstate->epc); |
if (s) |
symbol = s; |
panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol); |
} |
/** Try to find PTE for faulting address |
* |
* Try to find PTE for faulting address. |
* The AS->lock must be held on entry to this function. |
* |
* @param badvaddr Faulting virtual address. |
* |
* @return PTE on success, NULL otherwise. |
*/ |
pte_t *find_mapping_and_check(__address badvaddr) |
{ |
entry_hi_t hi; |
pte_t *pte; |
hi.value = cp0_entry_hi_read(); |
/* |
* Handler cannot succeed if the ASIDs don't match. |
*/ |
if (hi.asid != AS->asid) { |
printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); |
return NULL; |
} |
/* |
* Check if the mapping exists in page tables. |
*/ |
pte = page_mapping_find(badvaddr, AS->asid, 0); |
if (pte && pte->lo.v) { |
/* |
* Mapping found in page tables. |
* Immediately succeed. |
*/ |
return pte; |
} else { |
/* |
* Mapping not found in page tables. |
* Resort to higher-level page fault handler. |
*/ |
if (as_page_fault(badvaddr)) { |
/* |
* The higher-level page fault handler succeeded, |
* The mapping ought to be in place. |
*/ |
pte = page_mapping_find(badvaddr, AS->asid, 0); |
ASSERT(pte && pte->lo.v); |
return pte; |
} |
} |
/* |
* Handler cannot succeed if badvaddr has no mapping. |
*/ |
if (!pte) { |
printf("No such mapping.\n"); |
return NULL; |
} |
/* |
* Handler cannot succeed if the mapping is marked as invalid. |
*/ |
if (!pte->lo.v) { |
printf("Invalid mapping.\n"); |
return NULL; |
} |
return pte; |
} |
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn) |
{ |
lo->value = 0; |
lo->g = g; |
lo->v = v; |
lo->d = d; |
lo->c = c; |
lo->pfn = pfn; |
} |
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr) |
{ |
hi->value = (((addr/PAGE_SIZE)/2)*PAGE_SIZE*2); |
hi->asid = asid; |
} |
/** Print contents of TLB. */ |
void tlb_print(void) |
{ |
page_mask_t mask; |
entry_lo_t lo0, lo1; |
entry_hi_t hi, hi_save; |
int i; |
hi_save.value = cp0_entry_hi_read(); |
printf("TLB:\n"); |
for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
cp0_index_write(i); |
tlbr(); |
mask.value = cp0_pagemask_read(); |
hi.value = cp0_entry_hi_read(); |
lo0.value = cp0_entry_lo0_read(); |
lo1.value = cp0_entry_lo1_read(); |
printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n" |
"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n", |
i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn, |
lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
} |
cp0_entry_hi_write(hi_save.value); |
} |
/** Invalidate all not wired TLB entries. */ |
void tlb_invalidate_all(void) |
{ |
ipl_t ipl; |
entry_lo_t lo0, lo1; |
entry_hi_t hi_save; |
int i; |
hi_save.value = cp0_entry_hi_read(); |
ipl = interrupts_disable(); |
for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
cp0_index_write(i); |
tlbr(); |
lo0.value = cp0_entry_lo0_read(); |
lo1.value = cp0_entry_lo1_read(); |
lo0.v = 0; |
lo1.v = 0; |
cp0_entry_lo0_write(lo0.value); |
cp0_entry_lo1_write(lo1.value); |
tlbwi(); |
} |
interrupts_restore(ipl); |
cp0_entry_hi_write(hi_save.value); |
} |
/** Invalidate all TLB entries belonging to specified address space. |
* |
* @param asid Address space identifier. |
*/ |
void tlb_invalidate_asid(asid_t asid) |
{ |
ipl_t ipl; |
entry_lo_t lo0, lo1; |
entry_hi_t hi, hi_save; |
int i; |
ASSERT(asid != ASID_INVALID); |
hi_save.value = cp0_entry_hi_read(); |
ipl = interrupts_disable(); |
for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
cp0_index_write(i); |
tlbr(); |
hi.value = cp0_entry_hi_read(); |
if (hi.asid == asid) { |
lo0.value = cp0_entry_lo0_read(); |
lo1.value = cp0_entry_lo1_read(); |
lo0.v = 0; |
lo1.v = 0; |
cp0_entry_lo0_write(lo0.value); |
cp0_entry_lo1_write(lo1.value); |
tlbwi(); |
} |
} |
interrupts_restore(ipl); |
cp0_entry_hi_write(hi_save.value); |
} |
/** Invalidate TLB entries for specified page range belonging to specified address space. |
* |
* @param asid Address space identifier. |
* @param page First page whose TLB entry is to be invalidated. |
* @param cnt Number of entries to invalidate. |
*/ |
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
{ |
int i; |
ipl_t ipl; |
entry_lo_t lo0, lo1; |
entry_hi_t hi, hi_save; |
tlb_index_t index; |
ASSERT(asid != ASID_INVALID); |
hi_save.value = cp0_entry_hi_read(); |
ipl = interrupts_disable(); |
for (i = 0; i < cnt; i++) { |
hi.value = 0; |
prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
cp0_entry_hi_write(hi.value); |
tlbp(); |
index.value = cp0_index_read(); |
if (!index.p) { |
/* Entry was found, index register contains valid index. */ |
tlbr(); |
lo0.value = cp0_entry_lo0_read(); |
lo1.value = cp0_entry_lo1_read(); |
lo0.v = 0; |
lo1.v = 0; |
cp0_entry_lo0_write(lo0.value); |
cp0_entry_lo1_write(lo1.value); |
tlbwi(); |
} |
} |
interrupts_restore(ipl); |
cp0_entry_hi_write(hi_save.value); |
} |
/kernel/trunk/arch/mips32/src/mm/as.c |
---|
0,0 → 1,58 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch/mm/as.h> |
#include <arch/mm/tlb.h> |
#include <mm/tlb.h> |
#include <mm/as.h> |
#include <arch/cp0.h> |
#include <arch.h> |
/** Install address space. |
* |
* Install ASID. |
* |
* @param as Address space structure. |
*/ |
void as_install_arch(as_t *as) |
{ |
entry_hi_t hi; |
ipl_t ipl; |
/* |
* Install ASID. |
*/ |
hi.value = cp0_entry_hi_read(); |
ipl = interrupts_disable(); |
spinlock_lock(&as->lock); |
hi.asid = as->asid; |
cp0_entry_hi_write(hi.value); |
spinlock_unlock(&as->lock); |
interrupts_restore(ipl); |
} |
/kernel/trunk/arch/mips32/src/mm/frame.c |
---|
0,0 → 1,54 |
/* |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch/mm/frame.h> |
#include <mm/frame.h> |
#include <arch/asm/boot.h> |
#include <arch/mm/page.h> |
#include <config.h> |
#include <panic.h> |
#include <print.h> |
#include <arch/drivers/arc.h> |
/** Create memory zones |
* |
* If ARC is known, read information from ARC, otherwise |
* assume some defaults. |
* - blacklist first FRAME because there is an exception vector |
*/ |
void frame_arch_init(void) |
{ |
/* Blacklist first 4KB, exception vector */ |
frame_region_not_free(0, FRAME_SIZE); |
if (arc_enabled()) |
arc_frame_init(); |
else |
zone_create_in_region(KA2PA(KERNEL_LOAD_ADDRESS), |
(config.memory_size & ~(FRAME_SIZE-1))); |
} |
/kernel/trunk/arch/mips32/src/mm/page.c |
---|
0,0 → 1,49 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch/mm/page.h> |
#include <genarch/mm/page_pt.h> |
#include <arch/mm/frame.h> |
#include <mm/frame.h> |
#include <mm/page.h> |
#include <arch/types.h> |
#include <memstr.h> |
pte_t *PTL0 = NULL; |
void page_arch_init(void) |
{ |
__address ptl0; |
page_operations = &page_pt_operations; |
ptl0 = frame_alloc(FRAME_KA | FRAME_PANIC, ONE_FRAME, NULL); |
memsetb(ptl0, FRAME_SIZE, 0); |
SET_PTL0_ADDRESS(KA2PA(ptl0)); |
} |
/kernel/trunk/arch/mips32/src/asm.S |
---|
0,0 → 1,297 |
# |
# Copyright (C) 2003-2004 Jakub Jermar |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions |
# are met: |
# |
# - Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# - Redistributions in binary form must reproduce the above copyright |
# notice, this list of conditions and the following disclaimer in the |
# documentation and/or other materials provided with the distribution. |
# - The name of the author may not be used to endorse or promote products |
# derived from this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
#include <arch/asm/regname.h> |
.text |
.macro cp0_read reg |
mfc0 $2,\reg |
j $31 |
nop |
.endm |
.macro cp0_write reg |
mtc0 $4,\reg |
j $31 |
nop |
.endm |
.set noat |
.set noreorder |
.set nomacro |
.global cp0_index_read |
.global cp0_index_write |
.global cp0_random_read |
.global cp0_entry_lo0_read |
.global cp0_entry_lo0_write |
.global cp0_entry_lo1_read |
.global cp0_entry_lo1_write |
.global cp0_context_read |
.global cp0_context_write |
.global cp0_pagemask_read |
.global cp0_pagemask_write |
.global cp0_wired_read |
.global cp0_wired_write |
.global cp0_badvaddr_read |
.global cp0_count_read |
.global cp0_count_write |
.global cp0_entry_hi_read |
.global cp0_entry_hi_write |
.global cp0_compare_read |
.global cp0_compare_write |
.global cp0_status_read |
.global cp0_status_write |
.global cp0_cause_read |
.global cp0_cause_write |
.global cp0_epc_read |
.global cp0_epc_write |
.global cp0_prid_read |
cp0_index_read: cp0_read $0 |
cp0_index_write: cp0_write $0 |
cp0_random_read: cp0_read $1 |
cp0_entry_lo0_read: cp0_read $2 |
cp0_entry_lo0_write: cp0_write $2 |
cp0_entry_lo1_read: cp0_read $3 |
cp0_entry_lo1_write: cp0_write $3 |
cp0_context_read: cp0_read $4 |
cp0_context_write: cp0_write $4 |
cp0_pagemask_read: cp0_read $5 |
cp0_pagemask_write: cp0_write $5 |
cp0_wired_read: cp0_read $6 |
cp0_wired_write: cp0_write $6 |
cp0_badvaddr_read: cp0_read $8 |
cp0_count_read: cp0_read $9 |
cp0_count_write: cp0_write $9 |
cp0_entry_hi_read: cp0_read $10 |
cp0_entry_hi_write: cp0_write $10 |
cp0_compare_read: cp0_read $11 |
cp0_compare_write: cp0_write $11 |
cp0_status_read: cp0_read $12 |
cp0_status_write: cp0_write $12 |
cp0_cause_read: cp0_read $13 |
cp0_cause_write: cp0_write $13 |
cp0_epc_read: cp0_read $14 |
cp0_epc_write: cp0_write $14 |
cp0_prid_read: cp0_read $15 |
.global cpu_halt |
cpu_halt: |
j cpu_halt |
nop |
.global memsetb |
memsetb: |
j _memsetb |
nop |
.global memcpy |
memcpy: |
j _memcpy |
nop |
.macro fpu_gp_save reg ctx |
mfc1 $t0,$\reg |
sw $t0, \reg*4(\ctx) |
.endm |
.macro fpu_gp_restore reg ctx |
lw $t0, \reg*4(\ctx) |
mtc1 $t0,$\reg |
.endm |
.macro fpu_ct_save reg ctx |
cfc1 $t0,$1 |
sw $t0, (\reg+32)*4(\ctx) |
.endm |
.macro fpu_ct_restore reg ctx |
lw $t0, (\reg+32)*4(\ctx) |
ctc1 $t0,$\reg |
.endm |
.global fpu_context_save |
fpu_context_save: |
#ifdef HAVE_FPU |
fpu_gp_save 0,$a0 |
fpu_gp_save 1,$a0 |
fpu_gp_save 2,$a0 |
fpu_gp_save 3,$a0 |
fpu_gp_save 4,$a0 |
fpu_gp_save 5,$a0 |
fpu_gp_save 6,$a0 |
fpu_gp_save 7,$a0 |
fpu_gp_save 8,$a0 |
fpu_gp_save 9,$a0 |
fpu_gp_save 10,$a0 |
fpu_gp_save 11,$a0 |
fpu_gp_save 12,$a0 |
fpu_gp_save 13,$a0 |
fpu_gp_save 14,$a0 |
fpu_gp_save 15,$a0 |
fpu_gp_save 16,$a0 |
fpu_gp_save 17,$a0 |
fpu_gp_save 18,$a0 |
fpu_gp_save 19,$a0 |
fpu_gp_save 20,$a0 |
fpu_gp_save 21,$a0 |
fpu_gp_save 22,$a0 |
fpu_gp_save 23,$a0 |
fpu_gp_save 24,$a0 |
fpu_gp_save 25,$a0 |
fpu_gp_save 26,$a0 |
fpu_gp_save 27,$a0 |
fpu_gp_save 28,$a0 |
fpu_gp_save 29,$a0 |
fpu_gp_save 30,$a0 |
fpu_gp_save 31,$a0 |
fpu_ct_save 1,$a0 |
fpu_ct_save 2,$a0 |
fpu_ct_save 3,$a0 |
fpu_ct_save 4,$a0 |
fpu_ct_save 5,$a0 |
fpu_ct_save 6,$a0 |
fpu_ct_save 7,$a0 |
fpu_ct_save 8,$a0 |
fpu_ct_save 9,$a0 |
fpu_ct_save 10,$a0 |
fpu_ct_save 11,$a0 |
fpu_ct_save 12,$a0 |
fpu_ct_save 13,$a0 |
fpu_ct_save 14,$a0 |
fpu_ct_save 15,$a0 |
fpu_ct_save 16,$a0 |
fpu_ct_save 17,$a0 |
fpu_ct_save 18,$a0 |
fpu_ct_save 19,$a0 |
fpu_ct_save 20,$a0 |
fpu_ct_save 21,$a0 |
fpu_ct_save 22,$a0 |
fpu_ct_save 23,$a0 |
fpu_ct_save 24,$a0 |
fpu_ct_save 25,$a0 |
fpu_ct_save 26,$a0 |
fpu_ct_save 27,$a0 |
fpu_ct_save 28,$a0 |
fpu_ct_save 29,$a0 |
fpu_ct_save 30,$a0 |
fpu_ct_save 31,$a0 |
#endif |
j $ra |
nop |
.global fpu_context_restore |
fpu_context_restore: |
#ifdef HAVE_FPU |
fpu_gp_restore 0,$a0 |
fpu_gp_restore 1,$a0 |
fpu_gp_restore 2,$a0 |
fpu_gp_restore 3,$a0 |
fpu_gp_restore 4,$a0 |
fpu_gp_restore 5,$a0 |
fpu_gp_restore 6,$a0 |
fpu_gp_restore 7,$a0 |
fpu_gp_restore 8,$a0 |
fpu_gp_restore 9,$a0 |
fpu_gp_restore 10,$a0 |
fpu_gp_restore 11,$a0 |
fpu_gp_restore 12,$a0 |
fpu_gp_restore 13,$a0 |
fpu_gp_restore 14,$a0 |
fpu_gp_restore 15,$a0 |
fpu_gp_restore 16,$a0 |
fpu_gp_restore 17,$a0 |
fpu_gp_restore 18,$a0 |
fpu_gp_restore 19,$a0 |
fpu_gp_restore 20,$a0 |
fpu_gp_restore 21,$a0 |
fpu_gp_restore 22,$a0 |
fpu_gp_restore 23,$a0 |
fpu_gp_restore 24,$a0 |
fpu_gp_restore 25,$a0 |
fpu_gp_restore 26,$a0 |
fpu_gp_restore 27,$a0 |
fpu_gp_restore 28,$a0 |
fpu_gp_restore 29,$a0 |
fpu_gp_restore 30,$a0 |
fpu_gp_restore 31,$a0 |
fpu_ct_restore 1,$a0 |
fpu_ct_restore 2,$a0 |
fpu_ct_restore 3,$a0 |
fpu_ct_restore 4,$a0 |
fpu_ct_restore 5,$a0 |
fpu_ct_restore 6,$a0 |
fpu_ct_restore 7,$a0 |
fpu_ct_restore 8,$a0 |
fpu_ct_restore 9,$a0 |
fpu_ct_restore 10,$a0 |
fpu_ct_restore 11,$a0 |
fpu_ct_restore 12,$a0 |
fpu_ct_restore 13,$a0 |
fpu_ct_restore 14,$a0 |
fpu_ct_restore 15,$a0 |
fpu_ct_restore 16,$a0 |
fpu_ct_restore 17,$a0 |
fpu_ct_restore 18,$a0 |
fpu_ct_restore 19,$a0 |
fpu_ct_restore 20,$a0 |
fpu_ct_restore 21,$a0 |
fpu_ct_restore 22,$a0 |
fpu_ct_restore 23,$a0 |
fpu_ct_restore 24,$a0 |
fpu_ct_restore 25,$a0 |
fpu_ct_restore 26,$a0 |
fpu_ct_restore 27,$a0 |
fpu_ct_restore 28,$a0 |
fpu_ct_restore 29,$a0 |
fpu_ct_restore 30,$a0 |
fpu_ct_restore 31,$a0 |
#endif |
j $ra |
nop |
/kernel/trunk/arch/mips32/src/mips32.c |
---|
0,0 → 1,132 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch.h> |
#include <arch/cp0.h> |
#include <arch/exception.h> |
#include <arch/asm.h> |
#include <mm/as.h> |
#include <userspace.h> |
#include <arch/console.h> |
#include <memstr.h> |
#include <proc/thread.h> |
#include <print.h> |
#include <arch/interrupt.h> |
#include <arch/drivers/arc.h> |
#include <console/chardev.h> |
#include <arch/debugger.h> |
#include <arch/asm/regname.h> |
/* Size of the code jumping to the exception handler code |
* - J+NOP |
*/ |
#define EXCEPTION_JUMP_SIZE 8 |
#define TLB_EXC ((char *) 0x80000000) |
#define NORM_EXC ((char *) 0x80000180) |
#define CACHE_EXC ((char *) 0x80000100) |
void arch_pre_mm_init(void) |
{ |
/* It is not assumed by default */ |
interrupts_disable(); |
/* Initialize dispatch table */ |
exception_init(); |
interrupt_init(); |
arc_init(); |
/* Copy the exception vectors to the right places */ |
memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE); |
memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE); |
/* |
* Switch to BEV normal level so that exception vectors point to the kernel. |
* Clear the error level. |
*/ |
cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
/* |
* Mask all interrupts |
*/ |
cp0_mask_all_int(); |
/* |
* Unmask hardware clock interrupt. |
*/ |
cp0_unmask_int(TIMER_IRQ); |
/* |
* Start hardware clock. |
*/ |
cp0_compare_write(cp0_compare_value + cp0_count_read()); |
console_init(); |
debugger_init(); |
arc_print_memory_map(); |
arc_print_devices(); |
} |
void arch_post_mm_init(void) |
{ |
} |
void arch_pre_smp_init(void) |
{ |
} |
void arch_post_smp_init(void) |
{ |
} |
void userspace(void) |
{ |
/* EXL=1, UM=1, IE=1 */ |
cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
cp0_status_um_bit | |
cp0_status_ie_enabled_bit)); |
cp0_epc_write(UTEXT_ADDRESS); |
userspace_asm(USTACK_ADDRESS+PAGE_SIZE); |
while (1) |
; |
} |
/* Stack pointer saved when entering user mode */ |
/* TODO: How do we do it on SMP system???? */ |
__address supervisor_sp; |
void before_thread_runs_arch(void) |
{ |
supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
} |
/kernel/trunk/arch/mips32/src/debugger.c |
---|
0,0 → 1,379 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch/debugger.h> |
#include <memstr.h> |
#include <console/kconsole.h> |
#include <console/cmd.h> |
#include <symtab.h> |
#include <print.h> |
#include <panic.h> |
#include <arch.h> |
#include <arch/cp0.h> |
#include <func.h> |
bpinfo_t breakpoints[BKPOINTS_MAX]; |
SPINLOCK_INITIALIZE(bkpoint_lock); |
static int cmd_print_breakpoints(cmd_arg_t *argv); |
static cmd_info_t bkpts_info = { |
.name = "bkpts", |
.description = "Print breakpoint table.", |
.func = cmd_print_breakpoints, |
.argc = 0, |
}; |
static int cmd_del_breakpoint(cmd_arg_t *argv); |
static cmd_arg_t del_argv = { |
.type = ARG_TYPE_INT |
}; |
static cmd_info_t delbkpt_info = { |
.name = "delbkpt", |
.description = "delbkpt <number> - Delete breakpoint.", |
.func = cmd_del_breakpoint, |
.argc = 1, |
.argv = &del_argv |
}; |
static int cmd_add_breakpoint(cmd_arg_t *argv); |
static cmd_arg_t add_argv = { |
.type = ARG_TYPE_INT |
}; |
static cmd_info_t addbkpt_info = { |
.name = "addbkpt", |
.description = "addbkpt <&symbol> - new bkpoint. Break on J/Branch insts unsupported.", |
.func = cmd_add_breakpoint, |
.argc = 1, |
.argv = &add_argv |
}; |
static cmd_arg_t adde_argv[] = { |
{ .type = ARG_TYPE_INT }, |
{ .type = ARG_TYPE_INT } |
}; |
static cmd_info_t addbkpte_info = { |
.name = "addbkpte", |
.description = "addebkpte <&symbol> <&func> - new bkpoint. Call func(or Nothing if 0).", |
.func = cmd_add_breakpoint, |
.argc = 2, |
.argv = adde_argv |
}; |
static struct { |
__u32 andmask; |
__u32 value; |
}jmpinstr[] = { |
{0xf3ff0000, 0x41000000}, /* BCzF */ |
{0xf3ff0000, 0x41020000}, /* BCzFL */ |
{0xf3ff0000, 0x41010000}, /* BCzT */ |
{0xf3ff0000, 0x41030000}, /* BCzTL */ |
{0xfc000000, 0x10000000}, /* BEQ */ |
{0xfc000000, 0x50000000}, /* BEQL */ |
{0xfc1f0000, 0x04010000}, /* BEQL */ |
{0xfc1f0000, 0x04110000}, /* BGEZAL */ |
{0xfc1f0000, 0x04130000}, /* BGEZALL */ |
{0xfc1f0000, 0x04030000}, /* BGEZL */ |
{0xfc1f0000, 0x1c000000}, /* BGTZ */ |
{0xfc1f0000, 0x5c000000}, /* BGTZL */ |
{0xfc1f0000, 0x18000000}, /* BLEZ */ |
{0xfc1f0000, 0x58000000}, /* BLEZL */ |
{0xfc1f0000, 0x04000000}, /* BLTZ */ |
{0xfc1f0000, 0x04100000}, /* BLTZAL */ |
{0xfc1f0000, 0x04120000}, /* BLTZALL */ |
{0xfc1f0000, 0x04020000}, /* BLTZL */ |
{0xfc000000, 0x14000000}, /* BNE */ |
{0xfc000000, 0x54000000}, /* BNEL */ |
{0xfc000000, 0x08000000}, /* J */ |
{0xfc000000, 0x0c000000}, /* JAL */ |
{0xfc1f07ff, 0x00000009}, /* JALR */ |
{0,0} /* EndOfTable */ |
}; |
/** Test, if the given instruction is a jump or branch instruction |
* |
* @param instr Instruction code |
* @return true - it is jump instruction, false otherwise |
*/ |
static bool is_jump(__native instr) |
{ |
int i; |
for (i=0;jmpinstr[i].andmask;i++) { |
if ((instr & jmpinstr[i].andmask) == jmpinstr[i].value) |
return true; |
} |
return false; |
} |
/** Add new breakpoint to table */ |
int cmd_add_breakpoint(cmd_arg_t *argv) |
{ |
bpinfo_t *cur = NULL; |
ipl_t ipl; |
int i; |
if (argv->intval & 0x3) { |
printf("Not aligned instruction, forgot to use &symbol?\n"); |
return 1; |
} |
ipl = interrupts_disable(); |
spinlock_lock(&bkpoint_lock); |
/* Check, that the breakpoints do not conflict */ |
for (i=0; i<BKPOINTS_MAX; i++) { |
if (breakpoints[i].address == (__address)argv->intval) { |
printf("Duplicate breakpoint %d.\n", i); |
spinlock_unlock(&bkpoints_lock); |
return 0; |
} else if (breakpoints[i].address == (__address)argv->intval + sizeof(__native) || \ |
breakpoints[i].address == (__address)argv->intval - sizeof(__native)) { |
printf("Adjacent breakpoints not supported, conflict with %d.\n", i); |
spinlock_unlock(&bkpoints_lock); |
return 0; |
} |
} |
for (i=0; i<BKPOINTS_MAX; i++) |
if (!breakpoints[i].address) { |
cur = &breakpoints[i]; |
break; |
} |
if (!cur) { |
printf("Too many breakpoints.\n"); |
spinlock_unlock(&bkpoint_lock); |
interrupts_restore(ipl); |
return 0; |
} |
cur->address = (__address) argv->intval; |
printf("Adding breakpoint on address: %p\n", argv->intval); |
cur->instruction = ((__native *)cur->address)[0]; |
cur->nextinstruction = ((__native *)cur->address)[1]; |
if (argv == &add_argv) { |
cur->flags = 0; |
} else { /* We are add extended */ |
cur->flags = BKPOINT_FUNCCALL; |
cur->bkfunc = (void (*)(void *, struct exception_regdump *)) argv[1].intval; |
} |
if (is_jump(cur->instruction)) |
cur->flags |= BKPOINT_ONESHOT; |
cur->counter = 0; |
/* Set breakpoint */ |
*((__native *)cur->address) = 0x0d; |
spinlock_unlock(&bkpoint_lock); |
interrupts_restore(ipl); |
return 1; |
} |
/** Remove breakpoint from table */ |
int cmd_del_breakpoint(cmd_arg_t *argv) |
{ |
bpinfo_t *cur; |
ipl_t ipl; |
if (argv->intval < 0 || argv->intval > BKPOINTS_MAX) { |
printf("Invalid breakpoint number.\n"); |
return 0; |
} |
ipl = interrupts_disable(); |
spinlock_lock(&bkpoint_lock); |
cur = &breakpoints[argv->intval]; |
if (!cur->address) { |
printf("Breakpoint does not exist.\n"); |
spinlock_unlock(&bkpoint_lock); |
interrupts_restore(ipl); |
return 0; |
} |
if ((cur->flags & BKPOINT_INPROG) && (cur->flags & BKPOINT_ONESHOT)) { |
printf("Cannot remove one-shot breakpoint in-progress\n"); |
spinlock_unlock(&bkpoint_lock); |
interrupts_restore(ipl); |
return 0; |
} |
((__u32 *)cur->address)[0] = cur->instruction; |
((__u32 *)cur->address)[1] = cur->nextinstruction; |
cur->address = NULL; |
spinlock_unlock(&bkpoint_lock); |
interrupts_restore(ipl); |
return 1; |
} |
/** Print table of active breakpoints */ |
int cmd_print_breakpoints(cmd_arg_t *argv) |
{ |
int i; |
char *symbol; |
printf("Breakpoint table.\n"); |
for (i=0; i < BKPOINTS_MAX; i++) |
if (breakpoints[i].address) { |
symbol = get_symtab_entry(breakpoints[i].address); |
printf("%d. 0x%p in %s\n",i, |
breakpoints[i].address, symbol); |
printf(" Count(%d) ", breakpoints[i].counter); |
if (breakpoints[i].flags & BKPOINT_INPROG) |
printf("INPROG "); |
if (breakpoints[i].flags & BKPOINT_ONESHOT) |
printf("ONESHOT "); |
if (breakpoints[i].flags & BKPOINT_FUNCCALL) |
printf("FUNCCALL "); |
printf("\n"); |
} |
return 1; |
} |
/** Initialize debugger */ |
void debugger_init() |
{ |
int i; |
for (i=0; i<BKPOINTS_MAX; i++) |
breakpoints[i].address = NULL; |
cmd_initialize(&bkpts_info); |
if (!cmd_register(&bkpts_info)) |
panic("could not register command %s\n", bkpts_info.name); |
cmd_initialize(&delbkpt_info); |
if (!cmd_register(&delbkpt_info)) |
panic("could not register command %s\n", delbkpt_info.name); |
cmd_initialize(&addbkpt_info); |
if (!cmd_register(&addbkpt_info)) |
panic("could not register command %s\n", addbkpt_info.name); |
cmd_initialize(&addbkpte_info); |
if (!cmd_register(&addbkpte_info)) |
panic("could not register command %s\n", addbkpte_info.name); |
} |
/** Handle breakpoint |
* |
* Find breakpoint in breakpoint table. |
* If found, call kconsole, set break on next instruction and reexecute. |
* If we are on "next instruction", set it back on the first and reexecute. |
* If breakpoint not found in breakpoint table, call kconsole and start |
* next instruction. |
*/ |
void debugger_bpoint(struct exception_regdump *pstate) |
{ |
bpinfo_t *cur = NULL; |
__address fireaddr = pstate->epc; |
int i; |
/* test branch delay slot */ |
if (cp0_cause_read() & 0x80000000) |
panic("Breakpoint in branch delay slot not supported.\n"); |
spinlock_lock(&bkpoint_lock); |
for (i=0; i<BKPOINTS_MAX; i++) { |
/* Normal breakpoint */ |
if (fireaddr == breakpoints[i].address \ |
&& !(breakpoints[i].flags & BKPOINT_REINST)) { |
cur = &breakpoints[i]; |
break; |
} |
/* Reinst only breakpoint */ |
if ((breakpoints[i].flags & BKPOINT_REINST) \ |
&& (fireaddr ==breakpoints[i].address+sizeof(__native))) { |
cur = &breakpoints[i]; |
break; |
} |
} |
if (cur) { |
if (cur->flags & BKPOINT_REINST) { |
/* Set breakpoint on first instruction */ |
((__u32 *)cur->address)[0] = 0x0d; |
/* Return back the second */ |
((__u32 *)cur->address)[1] = cur->nextinstruction; |
cur->flags &= ~BKPOINT_REINST; |
spinlock_unlock(&bkpoint_lock); |
return; |
} |
if (cur->flags & BKPOINT_INPROG) |
printf("Warning: breakpoint recursion\n"); |
if (!(cur->flags & BKPOINT_FUNCCALL)) |
printf("***Breakpoint %d: 0x%p in %s.\n", i, |
fireaddr, get_symtab_entry(pstate->epc)); |
/* Return first instruction back */ |
((__u32 *)cur->address)[0] = cur->instruction; |
if (! (cur->flags & BKPOINT_ONESHOT)) { |
/* Set Breakpoint on next instruction */ |
((__u32 *)cur->address)[1] = 0x0d; |
cur->flags |= BKPOINT_REINST; |
} |
cur->flags |= BKPOINT_INPROG; |
} else { |
printf("***Breakpoint 0x%p in %s.\n", fireaddr, |
get_symtab_entry(fireaddr)); |
/* Move on to next instruction */ |
pstate->epc += 4; |
} |
cur->counter++; |
if (cur && (cur->flags & BKPOINT_FUNCCALL)) { |
/* Allow zero bkfunc, just for counting */ |
if (cur->bkfunc) |
cur->bkfunc(cur, pstate); |
} else { |
printf("***Type 'exit' to exit kconsole.\n"); |
/* This disables all other processors - we are not SMP, |
* actually this gets us to cpu_halt, if scheduler() is run |
* - we generally do not want scheduler to be run from debug, |
* so this is a good idea |
*/ |
atomic_set(&haltstate,1); |
spinlock_unlock(&bkpoint_lock); |
kconsole("debug"); |
spinlock_lock(&bkpoint_lock); |
atomic_set(&haltstate,0); |
} |
if (cur && cur->address == fireaddr && (cur->flags & BKPOINT_INPROG)) { |
/* Remove one-shot breakpoint */ |
if ((cur->flags & BKPOINT_ONESHOT)) |
cur->address = NULL; |
/* Remove in-progress flag */ |
cur->flags &= ~BKPOINT_INPROG; |
} |
spinlock_unlock(&bkpoint_lock); |
} |
/kernel/trunk/arch/mips32/src/drivers/serial.c |
---|
0,0 → 1,138 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <interrupt.h> |
#include <arch/cp0.h> |
#include <arch/drivers/serial.h> |
#include <console/chardev.h> |
#include <console/console.h> |
static chardev_t console; |
static serial_t sconf[SERIAL_MAX]; |
static bool kb_enabled; |
static void serial_write(chardev_t *d, const char ch) |
{ |
serial_t *sd = (serial_t *)d->data; |
if (ch == '\n') |
serial_write(d, '\r'); |
/* Wait until transmit buffer empty */ |
while (! (SERIAL_READ_LSR(sd->port) & (1<<TRANSMIT_EMPTY_BIT))) |
; |
SERIAL_WRITE(sd->port, ch); |
} |
static void serial_enable(chardev_t *d) |
{ |
kb_enabled = true; |
} |
static void serial_disable(chardev_t *d) |
{ |
kb_enabled = false; |
} |
int serial_init(void) |
{ |
int i = 0; |
if (SERIAL_READ_LSR(SERIAL_COM1) == 0x60) { |
sconf[i].port = SERIAL_COM1; |
sconf[i].irq = SERIAL_COM1_IRQ; |
/* Enable interrupt on available data */ |
i++; |
} |
return i; |
} |
/** Read character from serial port, wait until available */ |
static char serial_do_read(chardev_t *dev) |
{ |
serial_t *sd = (serial_t *)dev->data; |
char ch; |
while (!(SERIAL_READ_LSR(sd->port) & 1)) |
; |
ch = SERIAL_READ(sd->port); |
if (ch =='\r') |
ch = '\n'; |
return ch; |
} |
/** Process keyboard interrupt. Does not work in simics? */ |
static void serial_interrupt(int n, void *stack) |
{ |
serial_t *sd = (serial_t *)console.data; |
char ch; |
if (!(SERIAL_READ_LSR(sd->port) & 1)) |
return; |
ch = SERIAL_READ(sd->port); |
if (ch =='\r') |
ch = '\n'; |
chardev_push_character(&console, ch); |
} |
static chardev_operations_t serial_ops = { |
.resume = serial_enable, |
.suspend = serial_disable, |
.write = serial_write, |
.read = serial_do_read |
}; |
iroutine old_timer; |
/** Do polling on timer interrupt */ |
static void timer_replace(int n, void *stack) |
{ |
old_timer(n, stack); |
serial_interrupt(n, stack); |
} |
void serial_console(void) |
{ |
serial_t *sd = &sconf[0]; |
chardev_initialize("serial_console", &console, &serial_ops); |
console.data = sd; |
kb_enabled = true; |
// int_register(2, "serial_drvr", serial_interrupt); |
/* I don't know why, but the serial interrupts simply |
* don't work on simics |
*/ |
old_timer = int_register(TIMER_IRQ, "serial_drvr_poll", timer_replace); |
stdin = &console; |
stdout = &console; |
} |
/kernel/trunk/arch/mips32/src/drivers/arc.c |
---|
0,0 → 1,313 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch/drivers/arc.h> |
#include <arch/mm/page.h> |
#include <print.h> |
#include <arch.h> |
#include <arch/byteorder.h> |
#include <arch/mm/frame.h> |
#include <mm/frame.h> |
#include <interrupt.h> |
#include <align.h> |
#include <console/console.h> |
/* This is a good joke, SGI HAS different types than NT bioses... */ |
/* Here is the SGI type */ |
static char *basetypes[] = { |
"ExceptionBlock", |
"SystemParameterBlock", |
"FreeContiguous", |
"FreeMemory", |
"BadMemory", |
"LoadedProgram", |
"FirmwareTemporary", |
"FirmwarePermanent" |
}; |
static char *ctypes[] = { |
"ARC_type", |
"CPU_type", |
"FPU_type", |
"PrimaryICache", |
"PrimaryDCache", |
"SecondaryICache", |
"SecondaryDCache", |
"SecondaryCache", |
"Memory", |
"EISAAdapter", |
"TCAdapter", |
"SCSIAdapter", |
"DTIAdapter", |
"MultiFunctionAdapter", |
"DiskController", |
"TapeController", |
"CDROMController", |
"WORMController", |
"SerialController", |
"NetworkController", |
"DisplayController", |
"ParallelController", |
"PointerController", |
"KeyboardController", |
"AudioController", |
"OtherController", |
"DiskPeripheral", |
"FloppyDiskPeripheral", |
"TapePeripheral", |
"ModemPeripheral", |
"MonitorPeripheral", |
"PrinterPeripheral", |
"PointerPeripheral", |
"KeyboardPeripheral", |
"TerminalPeripheral", |
"OtherPeripheral", |
"LinePeripheral", |
"NetworkPeripheral" |
"OtherPeripheral", |
"XTalkAdapter", |
"PCIAdapter", |
"GIOAdapter", |
"TPUAdapter", |
"Anonymous" |
}; |
static arc_sbp *sbp = (arc_sbp *)PA2KA(0x1000); |
static arc_func_vector_t *arc_entry; |
static void arc_putchar(char ch); |
/** Return true if ARC is available */ |
int arc_enabled(void) |
{ |
return sbp != NULL; |
} |
static void arc_print_component(arc_component *c) |
{ |
int i; |
printf("%s: ",ctypes[c->type]); |
for (i=0;i < c->identifier_len;i++) |
arc_putchar(c->identifier[i]); |
arc_putchar('\n'); |
} |
void arc_print_devices(void) |
{ |
arc_component *c,*next; |
if (!arc_enabled()) |
return; |
c = arc_entry->getchild(NULL); |
while (c) { |
arc_print_component(c); |
next = arc_entry->getchild(c); |
while (!next) { |
next = arc_entry->getpeer(c); |
if (!next) |
c = arc_entry->getparent(c); |
if (!c) |
return; |
} |
c = next; |
} |
} |
void arc_print_memory_map(void) |
{ |
arc_memdescriptor_t *desc; |
if (!arc_enabled()) |
return; |
printf("Memory map:\n"); |
desc = arc_entry->getmemorydescriptor(NULL); |
while (desc) { |
printf("%s: %d (size: %dKB)\n",basetypes[desc->type], |
desc->basepage * ARC_FRAME, |
desc->basecount*ARC_FRAME/1024); |
desc = arc_entry->getmemorydescriptor(desc); |
} |
} |
/** Print charactor to console */ |
static void arc_putchar(char ch) |
{ |
__u32 cnt; |
ipl_t ipl; |
/* TODO: Should be spinlock? */ |
ipl = interrupts_disable(); |
arc_entry->write(1, &ch, 1, &cnt); |
interrupts_restore(ipl); |
} |
/** Initialize ARC structure |
* |
* @return 0 - ARC OK, -1 - ARC does not exist |
*/ |
int arc_init(void) |
{ |
if (sbp->signature != ARC_MAGIC) { |
sbp = NULL; |
return -1; |
} |
arc_entry = sbp->firmwarevector; |
arc_putchar('A'); |
arc_putchar('R'); |
arc_putchar('C'); |
arc_putchar('\n'); |
return 0; |
} |
static bool kbd_polling_enabled; |
static chardev_t console; |
/** Try to get character, return character or -1 if not available */ |
static void arc_keyboard_poll(void) |
{ |
char ch; |
__u32 count; |
long result; |
if (! kbd_polling_enabled) |
return; |
if (arc_entry->getreadstatus(0)) |
return; |
result = arc_entry->read(0, &ch, 1, &count); |
if (result || count!=1) { |
return; |
} |
if (ch == '\r') |
ch = '\n'; |
if (ch == 0x7f) |
ch = '\b'; |
chardev_push_character(&console, ch); |
} |
static char arc_read(chardev_t *dev) |
{ |
char ch; |
__u32 count; |
long result; |
result = arc_entry->read(0, &ch, 1, &count); |
if (result || count!=1) { |
printf("Error reading from ARC keyboard.\n"); |
cpu_halt(); |
} |
if (ch == '\r') |
return '\n'; |
if (ch == 0x7f) |
return '\b'; |
return ch; |
} |
static void arc_write(chardev_t *dev, const char ch) |
{ |
arc_putchar(ch); |
} |
static void arc_enable(chardev_t *dev) |
{ |
kbd_polling_enabled = true; |
} |
static void arc_disable(chardev_t *dev) |
{ |
kbd_polling_enabled = false; |
} |
static chardev_operations_t arc_ops = { |
.resume = arc_enable, |
.suspend = arc_disable, |
.write = arc_write, |
.read = arc_read |
}; |
iroutine old_timer; |
/** Do polling on timer interrupt */ |
static void timer_replace(int n, void *stack) |
{ |
arc_keyboard_poll(); |
old_timer(n, stack); |
arc_keyboard_poll(); |
} |
void arc_console(void) |
{ |
kbd_polling_enabled = true; |
chardev_initialize("arc_console", &console, &arc_ops); |
old_timer = int_register(TIMER_IRQ, "arc_kb_poll", timer_replace); |
stdin = &console; |
stdout = &console; |
} |
/* Initialize frame zones from ARC firmware. |
* In the future we may use even the FirmwareTemporary regions, |
* currently we use the FreeMemory (what about the LoadedProgram?) |
*/ |
void arc_frame_init(void) |
{ |
arc_memdescriptor_t *desc; |
int total = 0; |
__address base; |
size_t basesize; |
desc = arc_entry->getmemorydescriptor(NULL); |
while (desc) { |
if (desc->type == FreeMemory || |
desc->type == FreeContiguous) { |
base = desc->basepage*ARC_FRAME; |
basesize = desc->basecount*ARC_FRAME; |
if (base % FRAME_SIZE ) { |
basesize -= FRAME_SIZE - (base % FRAME_SIZE); |
base = ALIGN_UP(base, FRAME_SIZE); |
} |
basesize = ALIGN_DOWN(basesize, FRAME_SIZE); |
total += basesize; |
zone_create_in_region(base, basesize); |
} |
desc = arc_entry->getmemorydescriptor(desc); |
} |
config.memory_size = total; |
} |
/kernel/trunk/arch/mips32/src/drivers/msim.c |
---|
0,0 → 1,110 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <interrupt.h> |
#include <console/chardev.h> |
#include <arch/drivers/msim.h> |
#include <arch/cp0.h> |
#include <console/console.h> |
static chardev_t console; |
static void msim_write(chardev_t *dev, const char ch); |
static void msim_enable(chardev_t *dev); |
static void msim_disable(chardev_t *dev); |
static char msim_do_read(chardev_t *dev); |
static chardev_operations_t msim_ops = { |
.resume = msim_enable, |
.suspend = msim_disable, |
.write = msim_write, |
.read = msim_do_read, |
}; |
/** Putchar that works with MSIM & gxemul */ |
void msim_write(chardev_t *dev, const char ch) |
{ |
*((char *) MSIM_VIDEORAM) = ch; |
} |
/* Called from getc(). */ |
void msim_enable(chardev_t *dev) |
{ |
cp0_unmask_int(MSIM_KBD_IRQ); |
} |
/* Called from getc(). */ |
void msim_disable(chardev_t *dev) |
{ |
cp0_mask_int(MSIM_KBD_IRQ); |
} |
#include <print.h> |
/** Read character using polling, assume interrupts disabled */ |
static char msim_do_read(chardev_t *dev) |
{ |
char ch; |
while (1) { |
ch = *((volatile char *) MSIM_KBD_ADDRESS); |
if (ch) { |
if (ch == '\r') |
return '\n'; |
if (ch == 0x7f) |
return '\b'; |
return ch; |
} |
} |
} |
/** Process keyboard interrupt. */ |
static void msim_interrupt(int n, void *stack) |
{ |
char ch = 0; |
ch = *((char *) MSIM_KBD_ADDRESS); |
if (ch =='\r') |
ch = '\n'; |
if (ch == 0x7f) |
ch = '\b'; |
chardev_push_character(&console, ch); |
} |
/* Return console object representing msim console */ |
void msim_console(void) |
{ |
chardev_initialize("msim_console", &console, &msim_ops); |
int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt); |
cp0_unmask_int(MSIM_KBD_IRQ); |
stdin = &console; |
stdout = &console; |
} |
/kernel/trunk/arch/mips32/src/exception.c |
---|
0,0 → 1,193 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch/exception.h> |
#include <arch/interrupt.h> |
#include <panic.h> |
#include <arch/cp0.h> |
#include <arch/types.h> |
#include <arch.h> |
#include <debug.h> |
#include <proc/thread.h> |
#include <symtab.h> |
#include <print.h> |
#include <interrupt.h> |
#include <func.h> |
#include <console/kconsole.h> |
#include <arch/debugger.h> |
static char * exctable[] = { |
"Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store", |
"Address Error - load/instr. fetch", |
"Address Error - store", |
"Bus Error - fetch instruction", |
"Bus Error - data reference", |
"Syscall", |
"BreakPoint", |
"Reserved Instruction", |
"Coprocessor Unusable", |
"Arithmetic Overflow", |
"Trap", |
"Virtual Coherency - instruction", |
"Floating Point", |
NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
"WatchHi/WatchLo", /* 23 */ |
NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
"Virtual Coherency - data", |
}; |
static void print_regdump(struct exception_regdump *pstate) |
{ |
char *pcsymbol = ""; |
char *rasymbol = ""; |
char *s = get_symtab_entry(pstate->epc); |
if (s) |
pcsymbol = s; |
s = get_symtab_entry(pstate->ra); |
if (s) |
rasymbol = s; |
printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol, |
pstate->ra,rasymbol); |
} |
static void unhandled_exception(int n, void *data) |
{ |
struct exception_regdump *pstate = (struct exception_regdump *)data; |
print_regdump(pstate); |
panic("unhandled exception %s\n", exctable[n]); |
} |
static void breakpoint_exception(int n, void *data) |
{ |
struct exception_regdump *pstate = (struct exception_regdump *)data; |
#ifdef CONFIG_DEBUG |
debugger_bpoint(pstate); |
#else |
/* it is necessary to not re-execute BREAK instruction after |
returning from Exception handler |
(see page 138 in R4000 Manual for more information) */ |
pstate->epc += 4; |
#endif |
} |
static void tlbmod_exception(int n, void *data) |
{ |
struct exception_regdump *pstate = (struct exception_regdump *)data; |
tlb_modified(pstate); |
} |
static void tlbinv_exception(int n, void *data) |
{ |
struct exception_regdump *pstate = (struct exception_regdump *)data; |
tlb_invalid(pstate); |
} |
#ifdef CONFIG_FPU_LAZY |
static void cpuns_exception(int n, void *data) |
{ |
if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id) |
scheduler_fpu_lazy_request(); |
else |
panic("unhandled Coprocessor Unusable Exception\n"); |
} |
#endif |
static void interrupt_exception(int n, void *pstate) |
{ |
__u32 cause; |
int i; |
/* decode interrupt number and process the interrupt */ |
cause = (cp0_cause_read() >> 8) &0xff; |
for (i = 0; i < 8; i++) |
if (cause & (1 << i)) |
exc_dispatch(i+INT_OFFSET, pstate); |
} |
void exception(struct exception_regdump *pstate) |
{ |
int cause; |
int excno; |
ASSERT(CPU != NULL); |
/* |
* NOTE ON OPERATION ORDERING |
* |
* On entry, interrupts_disable() must be called before |
* exception bit is cleared. |
*/ |
interrupts_disable(); |
cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
cp0_status_um_bit)); |
/* Save pstate so that the threads can access it */ |
/* If THREAD->pstate is set, this is nested exception, |
* do not rewrite it |
*/ |
if (THREAD && !THREAD->pstate) |
THREAD->pstate = pstate; |
cause = cp0_cause_read(); |
excno = cp0_cause_excno(cause); |
/* Dispatch exception */ |
exc_dispatch(excno, pstate); |
/* Set to NULL, so that we can still support nested |
* exceptions |
* TODO: We should probably set EXL bit before this command, |
* nesting. On the other hand, if some exception occurs between |
* here and ERET, it won't set anything on the pstate anyway. |
*/ |
if (THREAD) |
THREAD->pstate = NULL; |
} |
void exception_init(void) |
{ |
int i; |
/* Clear exception table */ |
for (i=0;i < IVT_ITEMS; i++) |
exc_register(i, "undef", unhandled_exception); |
exc_register(EXC_Bp, "bkpoint", breakpoint_exception); |
exc_register(EXC_Mod, "tlb_mod", tlbmod_exception); |
exc_register(EXC_TLBL, "tlbinvl", tlbinv_exception); |
exc_register(EXC_TLBS, "tlbinvl", tlbinv_exception); |
exc_register(EXC_Int, "interrupt", interrupt_exception); |
#ifdef CONFIG_FPU_LAZY |
exc_register(EXC_CpU, "cpunus", cpuns_exception); |
#endif |
} |
/kernel/trunk/arch/mips32/src/cpu/cpu.c |
---|
0,0 → 1,129 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch/cpu.h> |
#include <cpu.h> |
#include <arch.h> |
#include <arch/cp0.h> |
#include <typedefs.h> |
#include <print.h> |
struct data_t { |
char *vendor; |
char *model; |
}; |
static struct data_t imp_data[] = { |
{ "Invalid", "Invalid" }, /* 0x00 */ |
{ "MIPS", "R2000" }, /* 0x01 */ |
{ "MIPS", "R3000" }, /* 0x02 */ |
{ "MIPS", "R6000" }, /* 0x03 */ |
{ "MIPS", " R4000/R4400" }, /* 0x04 */ |
{ "LSI Logic", "R3000" }, /* 0x05 */ |
{ "MIPS", "R6000A" }, /* 0x06 */ |
{ "IDT", "3051/3052" }, /* 0x07 */ |
{ "Invalid", "Invalid" }, /* 0x08 */ |
{ "MIPS", "R10000/T5" }, /* 0x09 */ |
{ "MIPS", "R4200" }, /* 0x0a */ |
{ "Unknown", "Unknown" }, /* 0x0b */ |
{ "Unknown", "Unknown" }, /* 0x0c */ |
{ "Invalid", "Invalid" }, /* 0x0d */ |
{ "Invalid", "Invalid" }, /* 0x0e */ |
{ "Invalid", "Invalid" }, /* 0x0f */ |
{ "MIPS", "R8000" }, /* 0x10 */ |
{ "Invalid", "Invalid" }, /* 0x11 */ |
{ "Invalid", "Invalid" }, /* 0x12 */ |
{ "Invalid", "Invalid" }, /* 0x13 */ |
{ "Invalid", "Invalid" }, /* 0x14 */ |
{ "Invalid", "Invalid" }, /* 0x15 */ |
{ "Invalid", "Invalid" }, /* 0x16 */ |
{ "Invalid", "Invalid" }, /* 0x17 */ |
{ "Invalid", "Invalid" }, /* 0x18 */ |
{ "Invalid", "Invalid" }, /* 0x19 */ |
{ "Invalid", "Invalid" }, /* 0x1a */ |
{ "Invalid", "Invalid" }, /* 0x1b */ |
{ "Invalid", "Invalid" }, /* 0x1c */ |
{ "Invalid", "Invalid" }, /* 0x1d */ |
{ "Invalid", "Invalid" }, /* 0x1e */ |
{ "Invalid", "Invalid" }, /* 0x1f */ |
{ "QED", "R4600" }, /* 0x20 */ |
{ "Sony", "R3000" }, /* 0x21 */ |
{ "Toshiba", "R3000" }, /* 0x22 */ |
{ "NKK", "R3000" }, /* 0x23 */ |
{ NULL, NULL } |
}; |
static struct data_t imp_data80[] = { |
{ "MIPS", "4Kc" }, /* 0x80 */ |
{"Invalid","Invalid"}, /* 0x81 */ |
{"Invalid","Invalid"}, /* 0x82 */ |
{"MIPS","4Km & 4Kp"}, /* 0x83 */ |
{ NULL, NULL} |
}; |
void cpu_arch_init(void) |
{ |
} |
void cpu_identify(void) |
{ |
CPU->arch.rev_num = cp0_prid_read() & 0xff; |
CPU->arch.imp_num = (cp0_prid_read() >> 8) & 0xff; |
} |
void cpu_print_report(cpu_t *m) |
{ |
struct data_t *data; |
int i; |
if (m->arch.imp_num & 0x80) { |
/* Count records */ |
for (i=0;imp_data80[i].vendor;i++) |
; |
if ((m->arch.imp_num & 0x7f) >= i) { |
printf("imp=%d\n",m->arch.imp_num); |
return; |
} |
data = &imp_data80[m->arch.imp_num & 0x7f]; |
} else { |
for (i=0;imp_data[i].vendor;i++) |
; |
if (m->arch.imp_num >= i) { |
printf("imp=%d\n",m->arch.imp_num); |
return; |
} |
data = &imp_data[m->arch.imp_num]; |
} |
printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n", |
m->id, data->vendor, data->model, m->arch.rev_num >> 4, |
m->arch.rev_num & 0xf, m->arch.imp_num); |
} |
/kernel/trunk/arch/mips32/src/interrupt.c |
---|
0,0 → 1,99 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <interrupt.h> |
#include <arch/interrupt.h> |
#include <arch/types.h> |
#include <arch.h> |
#include <arch/cp0.h> |
#include <time/clock.h> |
#include <arch/drivers/arc.h> |
/** Disable interrupts. |
* |
* @return Old interrupt priority level. |
*/ |
ipl_t interrupts_disable(void) |
{ |
ipl_t ipl = (ipl_t) cp0_status_read(); |
cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); |
return ipl; |
} |
/** Enable interrupts. |
* |
* @return Old interrupt priority level. |
*/ |
ipl_t interrupts_enable(void) |
{ |
ipl_t ipl = (ipl_t) cp0_status_read(); |
cp0_status_write(ipl | cp0_status_ie_enabled_bit); |
return ipl; |
} |
/** Restore interrupt priority level. |
* |
* @param ipl Saved interrupt priority level. |
*/ |
void interrupts_restore(ipl_t ipl) |
{ |
cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); |
} |
/** Read interrupt priority level. |
* |
* @return Current interrupt priority level. |
*/ |
ipl_t interrupts_read(void) |
{ |
return cp0_status_read(); |
} |
static void timer_exception(int n, void *stack) |
{ |
cp0_compare_write(cp0_count_read() + cp0_compare_value); |
clock(); |
} |
static void swint0(int n, void *stack) |
{ |
cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
} |
static void swint1(int n, void *stack) |
{ |
cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
} |
/* Initialize basic tables for exception dispatching */ |
void interrupt_init(void) |
{ |
int_register(TIMER_IRQ, "timer", timer_exception); |
int_register(0, "swint0", swint0); |
int_register(1, "swint1", swint1); |
} |
/kernel/trunk/arch/mips32/src/panic.S |
---|
0,0 → 1,48 |
# |
# Copyright (C) 2003-2004 Jakub Jermar |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions |
# are met: |
# |
# - Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# - Redistributions in binary form must reproduce the above copyright |
# notice, this list of conditions and the following disclaimer in the |
# documentation and/or other materials provided with the distribution. |
# - The name of the author may not be used to endorse or promote products |
# derived from this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
.text |
.set noat |
.set noreorder |
.set nomacro |
#include <arch/asm/regname.h> |
.global panic_printf |
/* From printf return directly to halt() */ |
panic_printf: |
jal printf |
nop |
j halt |
nop |
/* This code does not work, god knows why */ |
/* lui $ra, %hi(halt) |
j printf |
ori $ra, %lo(halt) */ |
/kernel/trunk/arch/mips32/src/console.c |
---|
0,0 → 1,43 |
/* |
* Copyright (C) 2005 Ondrej Palkovsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <console/console.h> |
#include <arch/console.h> |
#include <arch/drivers/arc.h> |
#include <arch/drivers/serial.h> |
#include <arch/drivers/msim.h> |
void console_init(void) |
{ |
if (arc_enabled()) { |
arc_console(); |
} else if (serial_init()) { |
serial_console(); |
} else |
msim_console(); |
} |
/kernel/trunk/arch/mips32/src/fpu_context.c |
---|
0,0 → 1,56 |
/* |
* Copyright (C) 2005 Jakub Vana |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
* |
*/ |
#include <fpu_context.h> |
#include <arch.h> |
#include <arch/cp0.h> |
#include <proc/thread.h> |
void fpu_disable(void) |
{ |
#ifdef HAVE_FPU |
cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit); |
if (THREAD && THREAD->pstate) |
THREAD->pstate->status &= ~cp0_status_fpu_bit; |
#endif |
} |
void fpu_enable(void) |
{ |
#ifdef HAVE_FPU |
cp0_status_write(cp0_status_read() | cp0_status_fpu_bit); |
if (THREAD && THREAD->pstate) |
THREAD->pstate->status |= cp0_status_fpu_bit; |
#endif |
} |
void fpu_init(void) |
{ |
/* TODO: Zero all registers */ |
} |
/kernel/trunk/arch/mips32/src/context.S |
---|
0,0 → 1,86 |
# |
# Copyright (C) 2003-2004 Jakub Jermar |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions |
# are met: |
# |
# - Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# - Redistributions in binary form must reproduce the above copyright |
# notice, this list of conditions and the following disclaimer in the |
# documentation and/or other materials provided with the distribution. |
# - The name of the author may not be used to endorse or promote products |
# derived from this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
#include <arch/asm/regname.h> |
#include <arch/context_offset.h> |
.text |
.set noat |
.set noreorder |
.set nomacro |
.global context_save_arch |
.global context_restore_arch |
.macro CONTEXT_STORE r |
sw $s0,OFFSET_S0(\r) |
sw $s1,OFFSET_S1(\r) |
sw $s2,OFFSET_S2(\r) |
sw $s3,OFFSET_S3(\r) |
sw $s4,OFFSET_S4(\r) |
sw $s5,OFFSET_S5(\r) |
sw $s6,OFFSET_S6(\r) |
sw $s7,OFFSET_S7(\r) |
sw $s8,OFFSET_S8(\r) |
sw $gp,OFFSET_GP(\r) |
sw $ra,OFFSET_PC(\r) |
sw $sp,OFFSET_SP(\r) |
.endm |
.macro CONTEXT_LOAD r |
lw $s0,OFFSET_S0(\r) |
lw $s1,OFFSET_S1(\r) |
lw $s2,OFFSET_S2(\r) |
lw $s3,OFFSET_S3(\r) |
lw $s4,OFFSET_S4(\r) |
lw $s5,OFFSET_S5(\r) |
lw $s6,OFFSET_S6(\r) |
lw $s7,OFFSET_S7(\r) |
lw $s8,OFFSET_S8(\r) |
lw $gp,OFFSET_GP(\r) |
lw $ra,OFFSET_PC(\r) |
lw $sp,OFFSET_SP(\r) |
.endm |
context_save_arch: |
CONTEXT_STORE $a0 |
# context_save returns 1 |
j $31 |
li $2, 1 |
context_restore_arch: |
CONTEXT_LOAD $a0 |
# context_restore returns 0 |
j $31 |
xor $2, $2 |
/kernel/trunk/arch/mips32/src/start.S |
---|
0,0 → 1,231 |
# |
# Copyright (C) 2003-2004 Jakub Jermar |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions |
# are met: |
# |
# - Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# - Redistributions in binary form must reproduce the above copyright |
# notice, this list of conditions and the following disclaimer in the |
# documentation and/or other materials provided with the distribution. |
# - The name of the author may not be used to endorse or promote products |
# derived from this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
#include <arch/asm/regname.h> |
#include <arch/mm/page.h> |
#include <arch/asm/boot.h> |
#include <arch/context_offset.h> |
.text |
.set noat |
.set noreorder |
.set nomacro |
.global kernel_image_start |
.global tlb_refill_entry |
.global cache_error_entry |
.global exception_entry |
.global userspace_asm |
# Save registers to space defined by \r |
# We will change $at on the way |
.macro REGISTERS_STORE r |
sw $at,EOFFSET_AT(\r) |
sw $v0,EOFFSET_V0(\r) |
sw $v1,EOFFSET_V1(\r) |
sw $a0,EOFFSET_A0(\r) |
sw $a1,EOFFSET_A1(\r) |
sw $a2,EOFFSET_A2(\r) |
sw $a3,EOFFSET_A3(\r) |
sw $t0,EOFFSET_T0(\r) |
sw $t1,EOFFSET_T1(\r) |
sw $t2,EOFFSET_T2(\r) |
sw $t3,EOFFSET_T3(\r) |
sw $t4,EOFFSET_T4(\r) |
sw $t5,EOFFSET_T5(\r) |
sw $t6,EOFFSET_T6(\r) |
sw $t7,EOFFSET_T7(\r) |
sw $t8,EOFFSET_T8(\r) |
sw $t9,EOFFSET_T9(\r) |
mflo $at |
sw $at, EOFFSET_LO(\r) |
mfhi $at |
sw $at, EOFFSET_HI(\r) |
sw $s0,EOFFSET_S0(\r) |
sw $s1,EOFFSET_S1(\r) |
sw $s2,EOFFSET_S2(\r) |
sw $s3,EOFFSET_S3(\r) |
sw $s4,EOFFSET_S4(\r) |
sw $s5,EOFFSET_S5(\r) |
sw $s6,EOFFSET_S6(\r) |
sw $s7,EOFFSET_S7(\r) |
sw $s8,EOFFSET_S8(\r) |
sw $gp,EOFFSET_GP(\r) |
sw $ra,EOFFSET_RA(\r) |
sw $sp,EOFFSET_SP(\r) |
mfc0 $at, $status |
sw $at,EOFFSET_STATUS(\r) |
mfc0 $at, $epc |
sw $at,EOFFSET_EPC(\r) |
.endm |
.macro REGISTERS_LOAD r |
lw $v0,EOFFSET_V0(\r) |
lw $v1,EOFFSET_V1(\r) |
lw $a0,EOFFSET_A0(\r) |
lw $a1,EOFFSET_A1(\r) |
lw $a2,EOFFSET_A2(\r) |
lw $a3,EOFFSET_A3(\r) |
lw $t0,EOFFSET_T0(\r) |
lw $t1,EOFFSET_T1(\r) |
lw $t2,EOFFSET_T2(\r) |
lw $t3,EOFFSET_T3(\r) |
lw $t4,EOFFSET_T4(\r) |
lw $t5,EOFFSET_T5(\r) |
lw $t6,EOFFSET_T6(\r) |
lw $t7,EOFFSET_T7(\r) |
lw $t8,EOFFSET_T8(\r) |
lw $t9,EOFFSET_T9(\r) |
lw $s0,EOFFSET_S0(\r) |
lw $s1,EOFFSET_S1(\r) |
lw $s2,EOFFSET_S2(\r) |
lw $s3,EOFFSET_S3(\r) |
lw $s4,EOFFSET_S4(\r) |
lw $s5,EOFFSET_S5(\r) |
lw $s6,EOFFSET_S6(\r) |
lw $s7,EOFFSET_S7(\r) |
lw $s8,EOFFSET_S8(\r) |
lw $gp,EOFFSET_GP(\r) |
lw $ra,EOFFSET_RA(\r) |
lw $at,EOFFSET_LO(\r) |
mtlo $at |
lw $at,EOFFSET_HI(\r) |
mthi $at |
lw $at,EOFFSET_STATUS(\r) |
mtc0 $at, $status |
lw $at,EOFFSET_EPC(\r) |
mtc0 $at, $epc |
lw $at,EOFFSET_AT(\r) |
lw $sp,EOFFSET_SP(\r) |
.endm |
# Move kernel stack pointer address to register K0 |
# - if we are in user mode, load the appropriate stack |
# address |
.macro KERNEL_STACK_TO_K0 |
# If we are in user mode |
mfc0 $k0, $status |
andi $k0, 0x10 |
beq $k0, $0, 1f |
add $k0, $sp, 0 |
# Move $k0 pointer to kernel stack |
lui $k0, %hi(supervisor_sp) |
ori $k0, $k0, %lo(supervisor_sp) |
# Move $k0 (superveisor_sp) |
lw $k0, 0($k0) |
1: |
.endm |
.org 0x0 |
kernel_image_start: |
/* Load temporary stack */ |
lui $sp, %hi(end_stack) |
ori $sp, $sp, %lo(end_stack) |
/* Not sure about this, but might be needed for PIC code???? */ |
lui $gp, 0x8000 |
jal main_bsp |
nop |
.space TEMP_STACK_SIZE |
end_stack: |
tlb_refill_entry: |
j tlb_refill_handler |
nop |
cache_error_entry: |
j cache_error_handler |
nop |
exception_entry: |
j exception_handler |
nop |
exception_handler: |
KERNEL_STACK_TO_K0 |
sub $k0, REGISTER_SPACE |
REGISTERS_STORE $k0 |
add $sp, $k0, 0 |
add $a0, $sp, 0 |
jal exception /* exception(register_space) */ |
nop |
REGISTERS_LOAD $sp |
# The $sp is automatically restored to former value |
eret |
nop |
tlb_refill_handler: |
KERNEL_STACK_TO_K0 |
sub $k0, REGISTER_SPACE |
REGISTERS_STORE $k0 |
add $sp, $k0, 0 |
add $a0, $sp, 0 |
jal tlb_refill /* tlb_refill(register_space) */ |
nop |
REGISTERS_LOAD $sp |
eret |
nop |
cache_error_handler: |
KERNEL_STACK_TO_K0 |
sub $sp, REGISTER_SPACE |
REGISTERS_STORE $sp |
add $sp, $k0, 0 |
jal cache_error |
nop |
REGISTERS_LOAD $sp |
eret |
nop |
userspace_asm: |
add $sp, $a0, 0 |
eret |
nop |
/kernel/trunk/arch/mips32/src/dummy.S |
---|
0,0 → 1,41 |
# |
# Copyright (C) 2003-2004 Jakub Jermar |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions |
# are met: |
# |
# - Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# - Redistributions in binary form must reproduce the above copyright |
# notice, this list of conditions and the following disclaimer in the |
# documentation and/or other materials provided with the distribution. |
# - The name of the author may not be used to endorse or promote products |
# derived from this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
.text |
.set noat |
.global calibrate_delay_loop |
.global asm_delay_loop |
.global dummy |
calibrate_delay_loop: |
asm_delay_loop: |
dummy: |
j $31 |
nop |
/kernel/trunk/arch/mips32/src/cache.c |
---|
0,0 → 1,35 |
/* |
* Copyright (C) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#include <arch/cache.h> |
#include <panic.h> |
void cache_error(void) |
{ |
panic("cache_error exception\n"); |
} |
/kernel/trunk/arch/mips32/_link.ld.in |
---|
0,0 → 1,60 |
/* |
* MIPS32 linker script |
* |
* kernel text |
* kernel data |
* |
*/ |
#undef mips |
#define mips mips |
OUTPUT_ARCH(mips) |
ENTRY(kernel_image_start) |
SECTIONS { |
. = KERNEL_LOAD_ADDRESS; |
.text : { |
ktext_start = .; |
*(.text); |
ktext_end = .; |
} |
.data : { |
kdata_start = .; |
*(.data); /* initialized data */ |
hardcoded_ktext_size = .; |
LONG(ktext_end - ktext_start); |
hardcoded_kdata_size = .; |
LONG(kdata_end - kdata_start); |
hardcoded_load_address = .; |
LONG(KERNEL_LOAD_ADDRESS); |
*(.rodata*); |
*(.sdata); |
*(.reginfo); |
/* Unfortunately IRIX does not allow us |
* to include this as a last section :-( |
* BSS/SBSS addresses will be wrong */ |
symbol_table = .; |
*(symtab.*); |
} |
_gp = . + 0x8000; |
.lit8 : { *(.lit8) } |
.lit4 : { *(.lit4) } |
.sbss : { |
*(.sbss); |
*(.scommon); |
} |
.bss : { |
*(.bss); /* uninitialized static variables */ |
*(COMMON); /* global variables */ |
} |
kdata_end = .; |
/DISCARD/ : { |
*(.mdebug*); |
*(.pdr); |
*(.comment); |
*(.note); |
} |
} |
/kernel/trunk/arch/mips32/boot/boot.S |
---|
0,0 → 1,43 |
# |
# Copyright (C) 2003-2004 Jakub Jermar |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions |
# are met: |
# |
# - Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# - Redistributions in binary form must reproduce the above copyright |
# notice, this list of conditions and the following disclaimer in the |
# documentation and/or other materials provided with the distribution. |
# - The name of the author may not be used to endorse or promote products |
# derived from this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
.text |
.set noat |
.set noreorder |
.set nomacro |
#define KERNEL_LOAD_ADDRESS 0x80100000 |
.global start |
start: |
lui $ra, KERNEL_LOAD_ADDRESS >> 16 |
ori $ra, KERNEL_LOAD_ADDRESS & 0xffff |
j $ra |
nop |
/kernel/trunk/arch/mips32/boot/Makefile |
---|
0,0 → 1,15 |
.PHONY: build clean |
CFLAGS = -nostdinc -nostdlib -fno-builtin -Werror-implicit-function-declaration -Wmissing-prototypes -Werror -O3 -mips3 -I../include |
build: boot.bin |
cp boot.bin ../../../load.bin |
boot.bin: boot.o |
$(LD) -e start -T _link.ld boot.o -o $@ |
boot.o: boot.S |
$(CC) $(CFLAGS) -c boot.S -o $@ |
clean: |
-rm -f boot.o boot.bin ../../../load.bin |
/kernel/trunk/arch/mips32/boot/_link.ld |
---|
0,0 → 1,8 |
/* OUTPUT_FORMAT(ecoff-littlemips) */ |
OUTPUT_FORMAT(binary) |
SECTIONS { |
.image 0x0: AT (0) { |
*(.text); |
*(.reginfo); |
} |
} |