42,13 → 42,13 |
#include <arch/asm.h> |
#include <typedefs.h> |
#include <panic.h> |
#include <print.h> |
#include <arch.h> |
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/** Invalidate all TLB entries. */ |
void tlb_invalidate_all(void) |
{ |
ipl_t ipl; |
__address adr; |
__u32 count1,count2,stride1,stride2; |
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60,14 → 60,11 |
stride1=PAL_PTCE_INFO_STRIDE1(); |
stride2=PAL_PTCE_INFO_STRIDE2(); |
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interrupts_disable(); |
ipl = interrupts_disable(); |
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for(i=0;i<count1;i++) |
{ |
for(j=0;j<count2;j++) |
{ |
asm volatile |
( |
for(i = 0; i < count1; i++) { |
for(j = 0; j < count2; j++) { |
__asm__ volatile ( |
"ptc.e %0;;" |
: |
:"r" (adr) |
77,7 → 74,7 |
adr+=stride1; |
} |
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interrupts_enable(); |
interrupts_restore(ipl); |
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srlz_d(); |
srlz_i(); |
89,7 → 86,6 |
*/ |
void tlb_invalidate_asid(asid_t asid) |
{ |
/* TODO */ |
tlb_invalidate_all(); |
} |
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96,8 → 92,6 |
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void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
{ |
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region_register rr; |
bool restore_rr = false; |
int b=0; |
121,79 → 115,60 |
srlz_i(); |
} |
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while(c>>=1) b++; |
while(c >>= 1) |
b++; |
b>>=1; |
__u64 ps; |
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switch(b) |
{ |
switch (b) { |
case 0: /*cnt 1-3*/ |
{ |
ps=PAGE_WIDTH; |
break; |
} |
case 1: /*cnt 4-15*/ |
{ |
/*cnt=((cnt-1)/4)+1;*/ |
ps=PAGE_WIDTH+2; |
va&=~((1<<ps)-1); |
break; |
} |
case 2: /*cnt 16-63*/ |
{ |
/*cnt=((cnt-1)/16)+1;*/ |
ps=PAGE_WIDTH+4; |
va&=~((1<<ps)-1); |
break; |
} |
case 3: /*cnt 64-255*/ |
{ |
/*cnt=((cnt-1)/64)+1;*/ |
ps=PAGE_WIDTH+6; |
va&=~((1<<ps)-1); |
break; |
} |
case 4: /*cnt 256-1023*/ |
{ |
/*cnt=((cnt-1)/256)+1;*/ |
ps=PAGE_WIDTH+8; |
va&=~((1<<ps)-1); |
break; |
} |
case 5: /*cnt 1024-4095*/ |
{ |
/*cnt=((cnt-1)/1024)+1;*/ |
ps=PAGE_WIDTH+10; |
va&=~((1<<ps)-1); |
break; |
} |
case 6: /*cnt 4096-16383*/ |
{ |
/*cnt=((cnt-1)/4096)+1;*/ |
ps=PAGE_WIDTH+12; |
va&=~((1<<ps)-1); |
break; |
} |
case 7: /*cnt 16384-65535*/ |
case 8: /*cnt 65536-(256K-1)*/ |
{ |
/*cnt=((cnt-1)/16384)+1;*/ |
ps=PAGE_WIDTH+14; |
va&=~((1<<ps)-1); |
break; |
} |
default: |
{ |
/*cnt=((cnt-1)/(16384*16))+1;*/ |
ps=PAGE_WIDTH+18; |
va&=~((1<<ps)-1); |
break; |
} |
} |
/*cnt+=(page!=va);*/ |
for(;va<(page+cnt*(PAGE_SIZE));va+=(1<<ps)) { |
__asm__ volatile |
( |
__asm__ volatile ( |
"ptc.l %0,%1;;" |
: |
: "r"(va), "r"(ps<<2) |
202,14 → 177,11 |
srlz_d(); |
srlz_i(); |
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if (restore_rr) { |
rr_write(VA2VRN(va), rr.word); |
srlz_d(); |
srlz_i(); |
} |
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} |
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506,7 → 478,7 |
* Forward the page fault to address space page fault handler. |
*/ |
if (!as_page_fault(va)) { |
panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid); |
panic("%s: va=%P, rid=%d, iip=%P\n", __FUNCTION__, va, rid, istate->cr_iip); |
} |
} |
} |
612,7 → 584,7 |
dtc_pte_copy(t); |
} else { |
if (!as_page_fault(va)) { |
panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid); |
panic("%s: va=%P, rid=%d\n", __FUNCTION__, va, rr.map.rid); |
} |
} |
} |