/kernel/trunk/arch/ia64/src/fpu_context.c |
---|
282,7 → 282,7 |
void fpu_enable(void) |
{ |
__u64 a = 0 ; |
uint64_t a = 0 ; |
asm volatile( |
"rsm %0;;" |
"srlz.i\n" |
304,7 → 304,7 |
void fpu_disable(void) |
{ |
__u64 a = 0 ; |
uint64_t a = 0 ; |
asm volatile( |
"ssm %0;;\n" |
"srlz.i\n" |
325,7 → 325,7 |
void fpu_init(void) |
{ |
__u64 a = 0 ; |
uint64_t a = 0 ; |
asm volatile |
( |
"mov %0=ar.fpsr;;\n" |
/kernel/trunk/arch/ia64/src/ddi/ddi.c |
---|
47,7 → 47,7 |
* |
* @return 0 on success or an error code from errno.h. |
*/ |
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size) |
int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) |
{ |
return 0; |
} |
/kernel/trunk/arch/ia64/src/proc/scheduler.c |
---|
50,11 → 50,11 |
/** Prepare kernel stack pointers in bank 0 r22 and r23 and make sure the stack is mapped in DTR. */ |
void before_thread_runs_arch(void) |
{ |
__address base; |
uintptr_t base; |
base = ALIGN_DOWN(config.base, 1<<KERNEL_PAGE_WIDTH); |
if ((__address) THREAD->kstack < base || (__address) THREAD->kstack > base + (1<<(KERNEL_PAGE_WIDTH))) { |
if ((uintptr_t) THREAD->kstack < base || (uintptr_t) THREAD->kstack > base + (1<<(KERNEL_PAGE_WIDTH))) { |
/* |
* Kernel stack of this thread is not mapped by DTR[TR_KERNEL]. |
* Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it. |
61,11 → 61,11 |
*/ |
/* purge DTR[TR_STACK1] and DTR[TR_STACK2] */ |
dtr_purge((__address) THREAD->kstack, PAGE_WIDTH+1); |
dtr_purge((uintptr_t) THREAD->kstack, PAGE_WIDTH+1); |
/* insert DTR[TR_STACK1] and DTR[TR_STACK2] */ |
dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1); |
dtlb_kernel_mapping_insert((__address) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2); |
dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1); |
dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2); |
} |
/* |
/kernel/trunk/arch/ia64/src/ia64.c |
---|
77,7 → 77,7 |
void arch_pre_mm_init(void) |
{ |
/* Set Interruption Vector Address (i.e. location of interruption vector table). */ |
iva_write((__address) &ivt); |
iva_write((uintptr_t) &ivt); |
srlz_d(); |
ski_init_console(); |
116,10 → 116,10 |
rsc.pl = PL_USER; |
rsc.mode = 3; /* eager mode */ |
switch_to_userspace((__address) kernel_uarg->uspace_entry, |
((__address) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT), |
((__address) kernel_uarg->uspace_stack)+PAGE_SIZE, |
(__address) kernel_uarg->uspace_uarg, |
switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry, |
((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT), |
((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE, |
(uintptr_t) kernel_uarg->uspace_uarg, |
psr.value, rsc.value); |
while (1) { |
131,7 → 131,7 |
* |
* We use r13 (a.k.a. tp) for this purpose. |
*/ |
__native sys_tls_set(__native addr) |
unative_t sys_tls_set(unative_t addr) |
{ |
return 0; |
} |
/kernel/trunk/arch/ia64/src/ski/ski.c |
---|
44,7 → 44,7 |
int kbd_uspace=0; |
static void ski_putchar(chardev_t *d, const char ch); |
static __s32 ski_getchar(void); |
static int32_t ski_getchar(void); |
/** Display character on debug console |
* |
78,9 → 78,9 |
* |
* @return ASCII code of pressed key or 0 if no key pressed. |
*/ |
__s32 ski_getchar(void) |
int32_t ski_getchar(void) |
{ |
__u64 ch; |
uint64_t ch; |
__asm__ volatile ( |
"mov r15=%1\n" |
92,7 → 92,7 |
: "r15", "r8" |
); |
return (__s32) ch; |
return (int32_t) ch; |
} |
/** |
/kernel/trunk/arch/ia64/src/cpu/cpu.c |
---|
51,10 → 51,10 |
void cpu_print_report(cpu_t *m) |
{ |
char *family_str; |
char vendor[2*sizeof(__u64)+1]; |
char vendor[2*sizeof(uint64_t)+1]; |
*((__u64 *) &vendor[0*sizeof(__u64)]) = CPU->arch.cpuid0; |
*((__u64 *) &vendor[1*sizeof(__u64)]) = CPU->arch.cpuid1; |
*((uint64_t *) &vendor[0*sizeof(uint64_t)]) = CPU->arch.cpuid0; |
*((uint64_t *) &vendor[1*sizeof(uint64_t)]) = CPU->arch.cpuid1; |
vendor[sizeof(vendor)-1] = '\0'; |
switch(m->arch.cpuid3.family) { |
/kernel/trunk/arch/ia64/src/mm/tlb.c |
---|
57,8 → 57,8 |
void tlb_invalidate_all(void) |
{ |
ipl_t ipl; |
__address adr; |
__u32 count1, count2, stride1, stride2; |
uintptr_t adr; |
uint32_t count1, count2, stride1, stride2; |
int i,j; |
101,7 → 101,7 |
} |
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
{ |
region_register rr; |
bool restore_rr = false; |
108,7 → 108,7 |
int b = 0; |
int c = cnt; |
__address va; |
uintptr_t va; |
va = page; |
rr.word = rr_read(VA2VRN(va)); |
129,7 → 129,7 |
while(c >>= 1) |
b++; |
b >>= 1; |
__u64 ps; |
uint64_t ps; |
switch (b) { |
case 0: /*cnt 1-3*/ |
201,7 → 201,7 |
* @param asid Address space identifier. |
* @param entry The rest of TLB entry as required by TLB insertion format. |
*/ |
void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) |
void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
{ |
tc_mapping_insert(va, asid, entry, true); |
} |
212,7 → 212,7 |
* @param asid Address space identifier. |
* @param entry The rest of TLB entry as required by TLB insertion format. |
*/ |
void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) |
void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
{ |
tc_mapping_insert(va, asid, entry, false); |
} |
224,7 → 224,7 |
* @param entry The rest of TLB entry as required by TLB insertion format. |
* @param dtc If true, insert into data translation cache, use instruction translation cache otherwise. |
*/ |
void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc) |
void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc) |
{ |
region_register rr; |
bool restore_rr = false; |
275,7 → 275,7 |
* @param entry The rest of TLB entry as required by TLB insertion format. |
* @param tr Translation register. |
*/ |
void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr) |
void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
{ |
tr_mapping_insert(va, asid, entry, false, tr); |
} |
287,7 → 287,7 |
* @param entry The rest of TLB entry as required by TLB insertion format. |
* @param tr Translation register. |
*/ |
void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr) |
void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
{ |
tr_mapping_insert(va, asid, entry, true, tr); |
} |
300,7 → 300,7 |
* @param dtr If true, insert into data translation register, use instruction translation register otherwise. |
* @param tr Translation register. |
*/ |
void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr) |
void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr) |
{ |
region_register rr; |
bool restore_rr = false; |
351,7 → 351,7 |
* @param dtr If true, insert into data translation register, use data translation cache otherwise. |
* @param tr Translation register if dtr is true, ignored otherwise. |
*/ |
void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr) |
void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr) |
{ |
tlb_entry_t entry; |
380,7 → 380,7 |
* @param page Virtual page address including VRN bits. |
* @param width Width of the purge in bits. |
*/ |
void dtr_purge(__address page, count_t width) |
void dtr_purge(uintptr_t page, count_t width) |
{ |
__asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2)); |
} |
444,11 → 444,11 |
* @param vector Interruption vector. |
* @param istate Structure with saved interruption state. |
*/ |
void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate) |
void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate) |
{ |
region_register rr; |
rid_t rid; |
__address va; |
uintptr_t va; |
pte_t *t; |
va = istate->cr_ifa; /* faulting address */ |
481,11 → 481,11 |
* @param vector Interruption vector. |
* @param istate Structure with saved interruption state. |
*/ |
void alternate_data_tlb_fault(__u64 vector, istate_t *istate) |
void alternate_data_tlb_fault(uint64_t vector, istate_t *istate) |
{ |
region_register rr; |
rid_t rid; |
__address va; |
uintptr_t va; |
pte_t *t; |
va = istate->cr_ifa; /* faulting address */ |
530,7 → 530,7 |
* @param vector Interruption vector. |
* @param istate Structure with saved interruption state. |
*/ |
void data_nested_tlb_fault(__u64 vector, istate_t *istate) |
void data_nested_tlb_fault(uint64_t vector, istate_t *istate) |
{ |
panic("%s\n", __FUNCTION__); |
} |
540,11 → 540,11 |
* @param vector Interruption vector. |
* @param istate Structure with saved interruption state. |
*/ |
void data_dirty_bit_fault(__u64 vector, istate_t *istate) |
void data_dirty_bit_fault(uint64_t vector, istate_t *istate) |
{ |
region_register rr; |
rid_t rid; |
__address va; |
uintptr_t va; |
pte_t *t; |
va = istate->cr_ifa; /* faulting address */ |
577,11 → 577,11 |
* @param vector Interruption vector. |
* @param istate Structure with saved interruption state. |
*/ |
void instruction_access_bit_fault(__u64 vector, istate_t *istate) |
void instruction_access_bit_fault(uint64_t vector, istate_t *istate) |
{ |
region_register rr; |
rid_t rid; |
__address va; |
uintptr_t va; |
pte_t *t; |
va = istate->cr_ifa; /* faulting address */ |
614,11 → 614,11 |
* @param vector Interruption vector. |
* @param istate Structure with saved interruption state. |
*/ |
void data_access_bit_fault(__u64 vector, istate_t *istate) |
void data_access_bit_fault(uint64_t vector, istate_t *istate) |
{ |
region_register rr; |
rid_t rid; |
__address va; |
uintptr_t va; |
pte_t *t; |
va = istate->cr_ifa; /* faulting address */ |
651,11 → 651,11 |
* @param vector Interruption vector. |
* @param istate Structure with saved interruption state. |
*/ |
void page_not_present(__u64 vector, istate_t *istate) |
void page_not_present(uint64_t vector, istate_t *istate) |
{ |
region_register rr; |
rid_t rid; |
__address va; |
uintptr_t va; |
pte_t *t; |
va = istate->cr_ifa; /* faulting address */ |
/kernel/trunk/arch/ia64/src/mm/vhpt.c |
---|
40,22 → 40,22 |
static vhpt_entry_t* vhpt_base; |
__address vhpt_set_up(void) |
uintptr_t vhpt_set_up(void) |
{ |
vhpt_base = frame_alloc(VHPT_WIDTH-FRAME_WIDTH,FRAME_KA | FRAME_ATOMIC); |
if(!vhpt_base) |
panic("Kernel configured with VHPT but no memory for table."); |
vhpt_invalidate_all(); |
return (__address) vhpt_base; |
return (uintptr_t) vhpt_base; |
} |
void vhpt_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) |
void vhpt_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
{ |
region_register rr_save, rr; |
index_t vrn; |
rid_t rid; |
__u64 tag; |
uint64_t tag; |
vhpt_entry_t *ventry; |
84,7 → 84,7 |
void vhpt_invalidate_all() |
{ |
memsetb((__address)vhpt_base,1<<VHPT_WIDTH,0); |
memsetb((uintptr_t)vhpt_base,1<<VHPT_WIDTH,0); |
} |
void vhpt_invalidate_asid(asid_t asid) |
/kernel/trunk/arch/ia64/src/mm/page.c |
---|
66,7 → 66,7 |
pta_register pta; |
int i; |
#ifdef CONFIG_VHPT |
__address vhpt_base; |
uintptr_t vhpt_base; |
#endif |
/* |
128,7 → 128,7 |
* |
* @return VHPT entry address. |
*/ |
vhpt_entry_t *vhpt_hash(__address page, asid_t asid) |
vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid) |
{ |
region_register rr_save, rr; |
index_t vrn; |
172,7 → 172,7 |
* |
* @return True if page and asid match the page and asid of t, false otherwise. |
*/ |
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v) |
bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v) |
{ |
region_register rr_save, rr; |
index_t vrn; |
216,12 → 216,12 |
* @param frame Physical address of the frame to wich page is mapped. |
* @param flags Different flags for the mapping. |
*/ |
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags) |
void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags) |
{ |
region_register rr_save, rr; |
index_t vrn; |
rid_t rid; |
__u64 tag; |
uint64_t tag; |
ASSERT(v); |
/kernel/trunk/arch/ia64/src/interrupt.c |
---|
119,10 → 119,10 |
"Reserved" |
}; |
static char *vector_to_string(__u16 vector); |
static char *vector_to_string(uint16_t vector); |
static void dump_interrupted_context(istate_t *istate); |
char *vector_to_string(__u16 vector) |
char *vector_to_string(uint16_t vector) |
{ |
ASSERT(vector <= VECTOR_MAX); |
152,7 → 152,7 |
printf("cr.ifa=%#018llx\t(%s)\n", istate->cr_ifa, ifa); |
} |
void general_exception(__u64 vector, istate_t *istate) |
void general_exception(uint64_t vector, istate_t *istate) |
{ |
char *desc = ""; |
188,19 → 188,19 |
void fpu_enable(void); |
void disabled_fp_register(__u64 vector, istate_t *istate) |
void disabled_fp_register(uint64_t vector, istate_t *istate) |
{ |
#ifdef CONFIG_FPU_LAZY |
scheduler_fpu_lazy_request(); |
#else |
fault_if_from_uspace(istate, "Interruption: %#hx (%s)", (__u16) vector, vector_to_string(vector)); |
fault_if_from_uspace(istate, "Interruption: %#hx (%s)", (uint16_t) vector, vector_to_string(vector)); |
dump_interrupted_context(istate); |
panic("Interruption: %#hx (%s)\n", (__u16) vector, vector_to_string(vector)); |
panic("Interruption: %#hx (%s)\n", (uint16_t) vector, vector_to_string(vector)); |
#endif |
} |
void nop_handler(__u64 vector, istate_t *istate) |
void nop_handler(uint64_t vector, istate_t *istate) |
{ |
} |
207,7 → 207,7 |
/** Handle syscall. */ |
int break_instruction(__u64 vector, istate_t *istate) |
int break_instruction(uint64_t vector, istate_t *istate) |
{ |
/* |
* Move to next instruction after BREAK. |
227,14 → 227,14 |
return -1; |
} |
void universal_handler(__u64 vector, istate_t *istate) |
void universal_handler(uint64_t vector, istate_t *istate) |
{ |
fault_if_from_uspace(istate,"Interruption: %#hx (%s)\n",(__u16) vector, vector_to_string(vector)); |
fault_if_from_uspace(istate,"Interruption: %#hx (%s)\n",(uint16_t) vector, vector_to_string(vector)); |
dump_interrupted_context(istate); |
panic("Interruption: %#hx (%s)\n", (__u16) vector, vector_to_string(vector)); |
panic("Interruption: %#hx (%s)\n", (uint16_t) vector, vector_to_string(vector)); |
} |
void external_interrupt(__u64 vector, istate_t *istate) |
void external_interrupt(uint64_t vector, istate_t *istate) |
{ |
cr_ivr_t ivr; |
254,7 → 254,7 |
} |
} |
void virtual_interrupt(__u64 irq,void *param) |
void virtual_interrupt(uint64_t irq,void *param) |
{ |
switch(irq) { |
case IRQ_KBD: |
267,7 → 267,7 |
} |
/* Reregister irq to be IPC-ready */ |
void irq_ipc_bind_arch(__native irq) |
void irq_ipc_bind_arch(unative_t irq) |
{ |
if(irq==IRQ_KBD) { |
kbd_uspace=1; |
/kernel/trunk/arch/ia64/src/drivers/it.c |
---|
71,8 → 71,8 |
/** Process Interval Timer interrupt. */ |
void it_interrupt(void) |
{ |
__s64 c; |
__s64 m; |
int64_t c; |
int64_t m; |
eoi_write(EOI); |