/kernel/trunk/arch/ia64/include/mm/page.h |
---|
30,25 → 30,12 |
#ifndef __ia64_PAGE_H__ |
#define __ia64_PAGE_H__ |
#ifndef __ASM__ |
#include <arch/mm/frame.h> |
#include <arch/barrier.h> |
#include <genarch/mm/page_ht.h> |
#include <arch/mm/asid.h> |
#include <arch/types.h> |
#include <typedefs.h> |
#include <debug.h> |
#endif |
#define PAGE_SIZE FRAME_SIZE |
#define PAGE_WIDTH FRAME_WIDTH |
#define KERNEL_PAGE_WIDTH 28 |
/** Bit width of the TLB-locked portion of kernel address space. */ |
#define KERNEL_PAGE_WIDTH 28 /* 256M */ |
#define SET_PTL0_ADDRESS_ARCH(x) /**< To be removed as situation permits. */ |
#define PPN_SHIFT 12 |
55,6 → 42,7 |
#define VRN_SHIFT 61 |
#define VRN_MASK (7LL << VRN_SHIFT) |
#define VA2VRN(va) ((va)>>VRN_SHIFT) |
#ifdef __ASM__ |
#define VRN_KERNEL 7 |
67,7 → 55,6 |
#define KA2PA(x) ((__address) (x-(VRN_KERNEL<<VRN_SHIFT))) |
#define PA2KA(x) ((__address) (x+(VRN_KERNEL<<VRN_SHIFT))) |
#define VHPT_WIDTH 20 /* 1M */ |
#define VHPT_SIZE (1 << VHPT_WIDTH) |
#define VHPT_BASE 0 /* Must be aligned to VHPT_SIZE */ |
87,13 → 74,16 |
#define AR_EXECUTE 0x1 |
#define AR_WRITE 0x2 |
#ifndef __ASM__ |
#define VA_REGION_INDEX 61 |
#include <arch/mm/frame.h> |
#include <arch/barrier.h> |
#include <genarch/mm/page_ht.h> |
#include <arch/mm/asid.h> |
#include <arch/types.h> |
#include <typedefs.h> |
#include <debug.h> |
#define VA_REGION(va) (va>>VA_REGION_INDEX) |
#ifndef __ASM__ |
struct vhpt_tag_info { |
unsigned long long tag : 63; |
unsigned ti : 1; |
155,8 → 145,6 |
__u64 word[4]; |
} vhpt_entry_t; |
typedef vhpt_entry_t tlb_entry_t; |
struct region_register_map { |
unsigned ve : 1; |
unsigned : 1; |
230,13 → 218,10 |
{ |
__u64 ret; |
ASSERT(i < REGION_REGISTERS); |
i=i<<VRN_SHIFT; |
__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i)); |
__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); |
return ret; |
} |
/** Write Region Register. |
* |
* @param i Region register index. |
245,11 → 230,11 |
static inline void rr_write(index_t i, __u64 v) |
{ |
ASSERT(i < REGION_REGISTERS); |
i=i<<VRN_SHIFT; |
__asm__ volatile ( |
"mov rr[%0] = %1;;\n" |
: |
: "r" (i), "r" (v)); |
"mov rr[%0] = %1\n" |
: |
: "r" (i << VRN_SHIFT), "r" (v) |
); |
} |
/** Read Page Table Register. |
280,10 → 265,6 |
extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v); |
extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags); |
#endif |
#endif |
/kernel/trunk/arch/ia64/include/mm/asid.h |
---|
34,27 → 34,24 |
#include <arch/types.h> |
typedef __u16 asid_t; |
typedef __u32 rid_t; |
#endif /* __ASM__ */ |
/** |
* Number of ia64 RIDs (Region Identifiers) per kernel ASID. |
* Note that some architectures may support more bits, |
* but those extra bits are not used by the kernel. |
*/ |
#endif |
#define RIDS_PER_ASID 7 |
#define RID_MAX 262143 /* 2^18 - 1 */ |
#define RID_KERNEL 0 |
#define RID_INVALID 1 |
#define ASID2RID(asid, vrn) (((asid)*RIDS_PER_ASID)+(vrn)) |
#define ASID2RID(asid, vrn) (((asid)>RIDS_PER_ASID)?(((asid)*RIDS_PER_ASID)+(vrn)):(asid)) |
#define RID2ASID(rid) ((rid)/RIDS_PER_ASID) |
#ifndef __ASM__ |
typedef __u32 rid_t; |
#endif |
#define ASID_MAX_ARCH (RID_MAX/RIDS_PER_ASID) |
#endif |
/kernel/trunk/arch/ia64/include/mm/tlb.h |
---|
38,14 → 38,47 |
#include <arch/types.h> |
#include <typedefs.h> |
extern void tc_mapping_insert(__address va, asid_t asid, vhpt_entry_t entry, bool dtc); |
extern void dtc_mapping_insert(__address va, asid_t asid, vhpt_entry_t entry); |
extern void itc_mapping_insert(__address va, asid_t asid, vhpt_entry_t entry); |
/** Data and instruction Translation Register indices. */ |
#define DTR_KERNEL 0 |
#define ITR_KERNEL 0 |
#define DTR_KSTACK 1 |
/** Portion of TLB insertion format data structure. */ |
union tlb_entry { |
__u64 word[2]; |
struct { |
/* Word 0 */ |
unsigned p : 1; /**< Present. */ |
unsigned : 1; |
unsigned ma : 3; /**< Memory attribute. */ |
unsigned a : 1; /**< Accessed. */ |
unsigned d : 1; /**< Dirty. */ |
unsigned pl : 2; /**< Privilege level. */ |
unsigned ar : 3; /**< Access rights. */ |
unsigned long long ppn : 38; /**< Physical Page Number, a.k.a. PFN. */ |
unsigned : 2; |
unsigned ed : 1; |
unsigned ig1 : 11; |
/* Word 1 */ |
unsigned : 2; |
unsigned ps : 6; /**< Page size will be 2^ps. */ |
unsigned key : 24; /**< Protection key, unused. */ |
unsigned : 32; |
} __attribute__ ((packed)); |
} __attribute__ ((packed)); |
typedef union tlb_entry tlb_entry_t; |
extern void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc); |
extern void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry); |
extern void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry); |
extern void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr); |
extern void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr); |
extern void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr); |
extern void dtlb_mapping_insert(__address page, __address frame, bool dtr, index_t tr); |
extern void alternate_instruction_tlb_fault(__u64 vector, struct exception_regdump *pstate); |
extern void alternate_data_tlb_fault(__u64 vector, struct exception_regdump *pstate); |
extern void data_nested_tlb_fault(__u64 vector, struct exception_regdump *pstate); |