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/kernel/trunk/arch/ia32/src/smp/smp.c
0,0 → 1,168
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <smp/smp.h>
#include <arch/smp/smp.h>
#include <arch/smp/mps.h>
#include <arch/smp/ap.h>
#include <genarch/acpi/acpi.h>
#include <genarch/acpi/madt.h>
#include <config.h>
#include <synch/waitq.h>
#include <synch/synch.h>
#include <arch/pm.h>
#include <func.h>
#include <panic.h>
#include <debug.h>
#include <arch/asm.h>
#include <mm/frame.h>
#include <mm/page.h>
#include <mm/heap.h>
#include <print.h>
#include <memstr.h>
#include <arch/i8259.h>
 
#ifdef CONFIG_SMP
 
static struct smp_config_operations *ops = NULL;
 
void smp_init(void)
{
if (acpi_madt) {
acpi_madt_parse();
ops = &madt_config_operations;
}
if (config.cpu_count == 1) {
mps_init();
ops = &mps_config_operations;
}
 
if (config.cpu_count > 1) {
page_mapping_insert((__address)l_apic, (__address)l_apic,
PAGE_NOT_CACHEABLE, 0);
page_mapping_insert((__address) io_apic,
(__address) io_apic,
PAGE_NOT_CACHEABLE, 0);
}
 
/*
* Must be initialized outside the kmp thread, since it is waited
* on before the kmp thread is created.
*/
waitq_initialize(&kmp_completion_wq);
 
}
 
/*
* Kernel thread for bringing up application processors. It becomes clear
* that we need an arrangement like this (AP's being initialized by a kernel
* thread), for a thread has its dedicated stack. (The stack used during the
* BSP initialization (prior the very first call to scheduler()) will be used
* as an initialization stack for each AP.)
*/
void kmp(void *arg)
{
__address src, dst;
int i;
ASSERT(ops != NULL);
 
waitq_initialize(&ap_completion_wq);
 
/*
* We need to access data in frame 0.
* We boldly make use of kernel address space mapping.
*/
 
/*
* Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
*/
*((__u16 *) (PA2KA(0x467+0))) = ((__address) ap_boot) >> 4; /* segment */
*((__u16 *) (PA2KA(0x467+2))) = 0; /* offset */
/*
* Save 0xa to address 0xf of the CMOS RAM.
* BIOS will not do the POST after the INIT signal.
*/
outb(0x70,0xf);
outb(0x71,0xa);
 
pic_disable_irqs(0xffff);
apic_init();
 
for (i = 0; i < ops->cpu_count(); i++) {
struct descriptor *gdt_new;
/*
* Skip processors marked unusable.
*/
if (!ops->cpu_enabled(i))
continue;
 
/*
* The bootstrap processor is already up.
*/
if (ops->cpu_bootstrap(i))
continue;
 
if (ops->cpu_apic_id(i) == l_apic_id()) {
printf("%s: bad processor entry #%d, will not send IPI to myself\n", __FUNCTION__, i);
continue;
}
/*
* Prepare new GDT for CPU in question.
*/
if (!(gdt_new = (struct descriptor *) malloc(GDT_ITEMS*sizeof(struct descriptor))))
panic("couldn't allocate memory for GDT\n");
 
memcpy(gdt_new, gdt, GDT_ITEMS*sizeof(struct descriptor));
memsetb((__address)(&gdt_new[TSS_DES]), sizeof(struct descriptor), 0);
real_bootstrap_gdtr.base = KA2PA((__address) gdt_new);
gdtr.base = (__address) gdt_new;
 
if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) {
/*
* There may be just one AP being initialized at
* the time. After it comes completely up, it is
* supposed to wake us up.
*/
if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_BLOCKING) == ESYNCH_TIMEOUT)
printf("%s: waiting for cpu%d (APIC ID = %d) timed out\n", __FUNCTION__, config.cpu_active > i ? config.cpu_active : i, ops->cpu_apic_id(i));
} else
printf("INIT IPI for l_apic%d failed\n", ops->cpu_apic_id(i));
}
 
/*
* Wakeup the kinit thread so that
* system initialization can go on.
*/
waitq_wakeup(&kmp_completion_wq, WAKEUP_FIRST);
}
 
#endif /* CONFIG_SMP */
/kernel/trunk/arch/ia32/src/smp/mps.c
0,0 → 1,425
/*
* Copyright (C) 2001-2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#ifdef CONFIG_SMP
 
#include <config.h>
#include <print.h>
#include <debug.h>
#include <arch/smp/mps.h>
#include <arch/smp/apic.h>
#include <arch/smp/smp.h>
#include <func.h>
#include <arch/types.h>
#include <typedefs.h>
#include <cpu.h>
#include <arch/asm.h>
#include <arch/bios/bios.h>
#include <mm/frame.h>
 
/*
* MultiProcessor Specification detection code.
*/
 
#define FS_SIGNATURE 0x5f504d5f
#define CT_SIGNATURE 0x504d4350
 
int mps_fs_check(__u8 *base);
int mps_ct_check(void);
 
int configure_via_ct(void);
int configure_via_default(__u8 n);
 
int ct_processor_entry(struct __processor_entry *pr);
void ct_bus_entry(struct __bus_entry *bus);
void ct_io_apic_entry(struct __io_apic_entry *ioa);
void ct_io_intr_entry(struct __io_intr_entry *iointr);
void ct_l_intr_entry(struct __l_intr_entry *lintr);
 
void ct_extended_entries(void);
 
static struct mps_fs *fs;
static struct mps_ct *ct;
 
struct __processor_entry *processor_entries = NULL;
struct __bus_entry *bus_entries = NULL;
struct __io_apic_entry *io_apic_entries = NULL;
struct __io_intr_entry *io_intr_entries = NULL;
struct __l_intr_entry *l_intr_entries = NULL;
 
int processor_entry_cnt = 0;
int bus_entry_cnt = 0;
int io_apic_entry_cnt = 0;
int io_intr_entry_cnt = 0;
int l_intr_entry_cnt = 0;
 
waitq_t ap_completion_wq;
waitq_t kmp_completion_wq;
 
 
/*
* Implementation of IA-32 SMP configuration interface.
*/
static count_t get_cpu_count(void);
static bool is_cpu_enabled(index_t i);
static bool is_bsp(index_t i);
static __u8 get_cpu_apic_id(index_t i);
 
struct smp_config_operations mps_config_operations = {
.cpu_count = get_cpu_count,
.cpu_enabled = is_cpu_enabled,
.cpu_bootstrap = is_bsp,
.cpu_apic_id = get_cpu_apic_id
};
 
count_t get_cpu_count(void)
{
return processor_entry_cnt;
}
 
bool is_cpu_enabled(index_t i)
{
ASSERT(i < processor_entry_cnt);
return processor_entries[i].cpu_flags & 0x1;
}
 
bool is_bsp(index_t i)
{
ASSERT(i < processor_entry_cnt);
return processor_entries[i].cpu_flags & 0x2;
}
 
__u8 get_cpu_apic_id(index_t i)
{
ASSERT(i < processor_entry_cnt);
return processor_entries[i].l_apic_id;
}
 
 
/*
* Used to check the integrity of the MP Floating Structure.
*/
int mps_fs_check(__u8 *base)
{
int i;
__u8 sum;
for (i = 0, sum = 0; i < 16; i++)
sum += base[i];
return !sum;
}
 
/*
* Used to check the integrity of the MP Configuration Table.
*/
int mps_ct_check(void)
{
__u8 *base = (__u8 *) ct;
__u8 *ext = base + ct->base_table_length;
__u8 sum;
int i;
/* count the checksum for the base table */
for (i=0,sum=0; i < ct->base_table_length; i++)
sum += base[i];
if (sum)
return 0;
/* count the checksum for the extended table */
for (i=0,sum=0; i < ct->ext_table_length; i++)
sum += ext[i];
return sum == ct->ext_table_checksum;
}
 
void mps_init(void)
{
__u8 *addr[2] = { NULL, (__u8 *) PA2KA(0xf0000) };
int i, j, length[2] = { 1024, 64*1024 };
 
/*
* Find MP Floating Pointer Structure
* 1a. search first 1K of EBDA
* 1b. if EBDA is undefined, search last 1K of base memory
* 2. search 64K starting at 0xf0000
*/
 
addr[0] = (__u8 *) PA2KA(ebda ? ebda : 639 * 1024);
for (i = 0; i < 2; i++) {
for (j = 0; j < length[i]; j += 16) {
if (*((__u32 *) &addr[i][j]) == FS_SIGNATURE && mps_fs_check(&addr[i][j])) {
fs = (struct mps_fs *) &addr[i][j];
goto fs_found;
}
}
}
 
return;
fs_found:
printf("%P: MPS Floating Pointer Structure\n", fs);
 
if (fs->config_type == 0 && fs->configuration_table) {
if (fs->mpfib2 >> 7) {
printf("%s: PIC mode not supported\n", __FUNCTION__);
return;
}
 
ct = (struct mps_ct *)PA2KA((__address)fs->configuration_table);
config.cpu_count = configure_via_ct();
}
else
config.cpu_count = configure_via_default(fs->config_type);
 
return;
}
 
int configure_via_ct(void)
{
__u8 *cur;
int i, cnt;
if (ct->signature != CT_SIGNATURE) {
printf("%s: bad ct->signature\n", __FUNCTION__);
return 1;
}
if (!mps_ct_check()) {
printf("%s: bad ct checksum\n", __FUNCTION__);
return 1;
}
if (ct->oem_table) {
printf("%s: ct->oem_table not supported\n", __FUNCTION__);
return 1;
}
l_apic = (__u32 *)(__address)ct->l_apic;
 
cnt = 0;
cur = &ct->base_table[0];
for (i=0; i < ct->entry_count; i++) {
switch (*cur) {
/* Processor entry */
case 0:
processor_entries = processor_entries ? processor_entries : (struct __processor_entry *) cur;
processor_entry_cnt++;
cnt += ct_processor_entry((struct __processor_entry *) cur);
cur += 20;
break;
 
/* Bus entry */
case 1:
bus_entries = bus_entries ? bus_entries : (struct __bus_entry *) cur;
bus_entry_cnt++;
ct_bus_entry((struct __bus_entry *) cur);
cur += 8;
break;
/* I/O Apic */
case 2:
io_apic_entries = io_apic_entries ? io_apic_entries : (struct __io_apic_entry *) cur;
io_apic_entry_cnt++;
ct_io_apic_entry((struct __io_apic_entry *) cur);
cur += 8;
break;
/* I/O Interrupt Assignment */
case 3:
io_intr_entries = io_intr_entries ? io_intr_entries : (struct __io_intr_entry *) cur;
io_intr_entry_cnt++;
ct_io_intr_entry((struct __io_intr_entry *) cur);
cur += 8;
break;
 
/* Local Interrupt Assignment */
case 4:
l_intr_entries = l_intr_entries ? l_intr_entries : (struct __l_intr_entry *) cur;
l_intr_entry_cnt++;
ct_l_intr_entry((struct __l_intr_entry *) cur);
cur += 8;
break;
 
default:
/*
* Something is wrong. Fallback to UP mode.
*/
printf("%s: ct badness\n", __FUNCTION__);
return 1;
}
}
/*
* Process extended entries.
*/
ct_extended_entries();
return cnt;
}
 
int configure_via_default(__u8 n)
{
/*
* Not yet implemented.
*/
printf("%s: not supported\n", __FUNCTION__);
return 1;
}
 
 
int ct_processor_entry(struct __processor_entry *pr)
{
/*
* Ignore processors which are not marked enabled.
*/
if ((pr->cpu_flags & (1<<0)) == 0)
return 0;
apic_id_mask |= (1<<pr->l_apic_id);
return 1;
}
 
void ct_bus_entry(struct __bus_entry *bus)
{
#ifdef MPSCT_VERBOSE
char buf[7];
memcpy((void *) buf, (void *) bus->bus_type, 6);
buf[6] = 0;
printf("bus%d: %s\n", bus->bus_id, buf);
#endif
}
 
void ct_io_apic_entry(struct __io_apic_entry *ioa)
{
static int io_apic_count = 0;
 
/* this ioapic is marked unusable */
if (ioa->io_apic_flags & 1 == 0)
return;
if (io_apic_count++ > 0) {
/*
* Multiple IO APIC's are currently not supported.
*/
return;
}
io_apic = (__u32 *)(__address)ioa->io_apic;
}
 
//#define MPSCT_VERBOSE
void ct_io_intr_entry(struct __io_intr_entry *iointr)
{
#ifdef MPSCT_VERBOSE
switch (iointr->intr_type) {
case 0: printf("INT"); break;
case 1: printf("NMI"); break;
case 2: printf("SMI"); break;
case 3: printf("ExtINT"); break;
}
putchar(',');
switch (iointr->poel&3) {
case 0: printf("bus-like"); break;
case 1: printf("active high"); break;
case 2: printf("reserved"); break;
case 3: printf("active low"); break;
}
putchar(',');
switch ((iointr->poel>>2)&3) {
case 0: printf("bus-like"); break;
case 1: printf("edge-triggered"); break;
case 2: printf("reserved"); break;
case 3: printf("level-triggered"); break;
}
putchar(',');
printf("bus%d,irq%d", iointr->src_bus_id, iointr->src_bus_irq);
putchar(',');
printf("io_apic%d,pin%d", iointr->dst_io_apic_id, iointr->dst_io_apic_pin);
putchar('\n');
#endif
}
 
void ct_l_intr_entry(struct __l_intr_entry *lintr)
{
#ifdef MPSCT_VERBOSE
switch (lintr->intr_type) {
case 0: printf("INT"); break;
case 1: printf("NMI"); break;
case 2: printf("SMI"); break;
case 3: printf("ExtINT"); break;
}
putchar(',');
switch (lintr->poel&3) {
case 0: printf("bus-like"); break;
case 1: printf("active high"); break;
case 2: printf("reserved"); break;
case 3: printf("active low"); break;
}
putchar(',');
switch ((lintr->poel>>2)&3) {
case 0: printf("bus-like"); break;
case 1: printf("edge-triggered"); break;
case 2: printf("reserved"); break;
case 3: printf("level-triggered"); break;
}
putchar(',');
printf("bus%d,irq%d", lintr->src_bus_id, lintr->src_bus_irq);
putchar(',');
printf("l_apic%d,pin%d", lintr->dst_l_apic_id, lintr->dst_l_apic_pin);
putchar('\n');
#endif
}
 
void ct_extended_entries(void)
{
__u8 *ext = (__u8 *) ct + ct->base_table_length;
__u8 *cur;
 
for (cur = ext; cur < ext + ct->ext_table_length; cur += cur[CT_EXT_ENTRY_LEN]) {
switch (cur[CT_EXT_ENTRY_TYPE]) {
default:
printf("%P: skipping MP Configuration Table extended entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]);
break;
}
}
}
 
int mps_irq_to_pin(int irq)
{
int i;
for(i=0;i<io_intr_entry_cnt;i++) {
if (io_intr_entries[i].src_bus_irq == irq && io_intr_entries[i].intr_type == 0)
return io_intr_entries[i].dst_io_apic_pin;
}
return -1;
}
 
#endif /* CONFIG_SMP */
/kernel/trunk/arch/ia32/src/smp/ap.S
0,0 → 1,76
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#
# Init code for application processors.
#
 
.section K_TEXT_START_2, "ax"
 
#ifdef CONFIG_SMP
 
.global ap_boot
 
KTEXT=8
KDATA=16
 
# This piece of code is real-mode and is meant to be alligned at 4K boundary.
# The requirement for such an alignment comes from MP Specification's STARTUP IPI
# requirements.
 
.align 4096
ap_boot:
.code16
cli
xorw %ax, %ax
movw %ax, %ds
 
lgdt real_bootstrap_gdtr_boot # initialize Global Descriptor Table register
movl %cr0, %eax
orl $1, %eax
movl %eax, %cr0 # switch to protected mode
jmpl $KTEXT, $jump_to_kernel
jump_to_kernel:
.code32
movw $KDATA, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movl $(ctx-0x80000000), %eax # KA2PA((__address) &ctx)
movl (%eax), %esp
subl $0x80000000, %esp # KA2PA(ctx.sp)
 
call map_kernel # map kernel and turn paging on
addl $0x80000000, %esp # PA2KA(ctx.sp)
jmpl $KTEXT, $main_ap
 
#endif /* CONFIG_SMP */
/kernel/trunk/arch/ia32/src/smp/ipi.c
0,0 → 1,39
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#ifdef CONFIG_SMP
 
#include <smp/ipi.h>
#include <arch/smp/apic.h>
 
void ipi_broadcast_arch(int ipi)
{
(void) l_apic_broadcast_custom_ipi((__u8) ipi);
}
 
#endif /* CONFIG_SMP */
/kernel/trunk/arch/ia32/src/smp/apic.c
0,0 → 1,419
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <mm/page.h>
#include <time/delay.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef CONFIG_SMP
 
/*
* This is functional, far-from-general-enough interface to the APIC.
* Advanced Programmable Interrupt Controller for MP systems.
* Tested on:
* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
* Simics 2.0.28 - Simics 2.2.14 2-4 CPUs
* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
*/
 
/*
* These variables either stay configured as initilalized, or are changed by
* the MP configuration code.
*
* Pay special attention to the volatile keyword. Without it, gcc -O2 would
* optimize the code too much and accesses to l_apic and io_apic, that must
* always be 32-bit, would use byte oriented instructions.
*/
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
 
__u32 apic_id_mask = 0;
 
int apic_poll_errors(void);
 
void apic_init(void)
{
__u32 tmp, id, i;
 
trap_register(VECTOR_APIC_SPUR, apic_spurious);
 
enable_irqs_function = io_apic_enable_irqs;
disable_irqs_function = io_apic_disable_irqs;
eoi_function = l_apic_eoi;
/*
* Configure interrupt routing.
* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
* Other interrupts will be forwarded to the lowest priority CPU.
*/
io_apic_disable_irqs(0xffff);
trap_register(VECTOR_CLK, l_apic_timer_interrupt);
for (i=1; i<16; i++) {
int pin;
if ((pin = mps_irq_to_pin(i)) != -1)
io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
}
 
/*
* Ensure that io_apic has unique ID.
*/
tmp = io_apic_read(IOAPICID);
id = (tmp >> 24) & 0xf;
if ((1<<id) & apic_id_mask) {
int i;
for (i=0; i<15; i++) {
if (!((1<<i) & apic_id_mask)) {
io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
break;
}
}
}
 
/*
* Configure the BSP's lapic.
*/
l_apic_init();
l_apic_debug();
}
 
void apic_spurious(__u8 n, __native stack[])
{
printf("cpu%d: APIC spurious interrupt\n", CPU->id);
}
 
int apic_poll_errors(void)
{
__u32 esr;
esr = l_apic[ESR] & ~ESRClear;
if ((esr>>0) & 1)
printf("Send CS Error\n");
if ((esr>>1) & 1)
printf("Receive CS Error\n");
if ((esr>>2) & 1)
printf("Send Accept Error\n");
if ((esr>>3) & 1)
printf("Receive Accept Error\n");
if ((esr>>5) & 1)
printf("Send Illegal Vector\n");
if ((esr>>6) & 1)
printf("Received Illegal Vector\n");
if ((esr>>7) & 1)
printf("Illegal Register Address\n");
 
return !esr;
}
 
/*
* Send all CPUs excluding CPU IPI vector.
*/
int l_apic_broadcast_custom_ipi(__u8 vector)
{
__u32 lo;
 
/*
* Read the ICR register in and zero all non-reserved fields.
*/
lo = l_apic[ICRlo] & ICRloClear;
 
lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector;
l_apic[ICRlo] = lo;
 
lo = l_apic[ICRlo] & ICRloClear;
if (lo & SEND_PENDING)
printf("IPI is pending.\n");
 
return apic_poll_errors();
}
 
/*
* Universal Start-up Algorithm for bringing up the AP processors.
*/
int l_apic_send_init_ipi(__u8 apicid)
{
__u32 lo, hi;
int i;
 
/*
* Read the ICR register in and zero all non-reserved fields.
*/
lo = l_apic[ICRlo] & ICRloClear;
hi = l_apic[ICRhi] & ICRhiClear;
lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
hi |= apicid << 24;
l_apic[ICRhi] = hi;
l_apic[ICRlo] = lo;
 
/*
* According to MP Specification, 20us should be enough to
* deliver the IPI.
*/
delay(20);
 
if (!apic_poll_errors()) return 0;
 
lo = l_apic[ICRlo] & ICRloClear;
if (lo & SEND_PENDING)
printf("IPI is pending.\n");
 
l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
 
/*
* Wait 10ms as MP Specification specifies.
*/
delay(10000);
 
if (!is_82489DX_apic(l_apic[LAVR])) {
/*
* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
*/
for (i = 0; i<2; i++) {
lo = l_apic[ICRlo] & ICRloClear;
lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
delay(200);
}
}
return apic_poll_errors();
}
 
void l_apic_init(void)
{
__u32 tmp, t1, t2;
 
l_apic[LVT_Err] |= (1<<16);
l_apic[LVT_LINT0] |= (1<<16);
l_apic[LVT_LINT1] |= (1<<16);
 
tmp = l_apic[SVR] & SVRClear;
l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
 
l_apic[TPR] &= TPRClear;
 
if (CPU->arch.family >= 6)
enable_l_apic_in_msr();
tmp = l_apic[ICRlo] & ICRloClear;
l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
/*
* Program the timer for periodic mode and respective vector.
*/
 
l_apic[TDCR] &= TDCRClear;
l_apic[TDCR] |= 0xb;
tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
l_apic[LVT_Tm] = tmp & ~(1<<16);
 
t1 = l_apic[CCRT];
l_apic[ICRT] = 0xffffffff;
 
while (l_apic[CCRT] == t1)
;
t1 = l_apic[CCRT];
delay(1000);
t2 = l_apic[CCRT];
l_apic[ICRT] = t1-t2;
}
 
void l_apic_eoi(void)
{
l_apic[EOI] = 0;
}
 
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
int i, lint;
 
printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
printf("LVT_Tm: ");
if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');
if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
printf("%B\n", l_apic[LVT_Tm] & 0xff);
for (i=0; i<2; i++) {
lint = i ? LVT_LINT1 : LVT_LINT0;
printf("LVT_LINT%d: ", i);
if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
printf("%d", l_apic[lint] & (1<<14)); putchar(',');
printf("%d", l_apic[lint] & (1<<13)); putchar(',');
if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
switch ((l_apic[lint]>>8)&7) {
case 0: printf("fixed"); break;
case 4: printf("NMI"); break;
case 7: printf("ExtINT"); break;
}
putchar(',');
printf("%B\n", l_apic[lint] & 0xff);
}
 
printf("LVT_Err: ");
if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
printf("%B\n", l_apic[LVT_Err] & 0xff);
 
/*
* This register is supported only on P6 and higher.
*/
if (CPU->arch.family > 5) {
printf("LVT_PCINT: ");
if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
switch ((l_apic[LVT_PCINT] >> 8)&7) {
case 0: printf("fixed"); break;
case 4: printf("NMI"); break;
case 7: printf("ExtINT"); break;
}
putchar(',');
printf("%B\n", l_apic[LVT_PCINT] & 0xff);
}
#endif
}
 
void l_apic_timer_interrupt(__u8 n, __native stack[])
{
l_apic_eoi();
clock();
}
 
__u8 l_apic_id(void)
{
return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
}
 
__u32 io_apic_read(__u8 address)
{
__u32 tmp;
tmp = io_apic[IOREGSEL] & ~0xf;
io_apic[IOREGSEL] = tmp | address;
return io_apic[IOWIN];
}
 
void io_apic_write(__u8 address, __u32 x)
{
__u32 tmp;
 
tmp = io_apic[IOREGSEL] & ~0xf;
io_apic[IOREGSEL] = tmp | address;
io_apic[IOWIN] = x;
}
 
void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
{
__u32 reglo, reghi;
int dlvr = 0;
if (flags & LOPRI)
dlvr = 1;
reglo = io_apic_read(IOREDTBL + signal*2);
reghi = io_apic_read(IOREDTBL + signal*2 + 1);
reghi &= ~0x0f000000;
reghi |= (dest<<24);
 
reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */
reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v;
 
io_apic_write(IOREDTBL + signal*2, reglo);
io_apic_write(IOREDTBL + signal*2 + 1, reghi);
}
 
void io_apic_disable_irqs(__u16 irqmask)
{
int i,pin;
__u32 reglo;
for (i=0;i<16;i++) {
if ((irqmask>>i) & 1) {
/*
* Mask the signal input in IO APIC if there is a
* mapping for the respective IRQ number.
*/
pin = mps_irq_to_pin(i);
if (pin != -1) {
reglo = io_apic_read(IOREDTBL + pin*2);
reglo |= (1<<16);
io_apic_write(IOREDTBL + pin*2,reglo);
}
}
}
}
 
void io_apic_enable_irqs(__u16 irqmask)
{
int i,pin;
__u32 reglo;
for (i=0;i<16;i++) {
if ((irqmask>>i) & 1) {
/*
* Unmask the signal input in IO APIC if there is a
* mapping for the respective IRQ number.
*/
pin = mps_irq_to_pin(i);
if (pin != -1) {
reglo = io_apic_read(IOREDTBL + pin*2);
reglo &= ~(1<<16);
io_apic_write(IOREDTBL + pin*2,reglo);
}
}
}
 
}
 
#endif /* CONFIG_SMP */
/kernel/trunk/arch/ia32/src/mm/page.c
0,0 → 1,78
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/types.h>
#include <config.h>
#include <func.h>
#include <mm/frame.h>
#include <mm/page.h>
#include <arch/mm/page.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <synch/spinlock.h>
#include <debug.h>
#include <memstr.h>
#include <print.h>
 
__address bootstrap_dba;
 
void page_arch_init(void)
{
__address dba;
__u32 i;
 
if (config.cpu_active == 1) {
dba = frame_alloc(FRAME_KA | FRAME_PANIC);
memsetb(dba, PAGE_SIZE, 0);
 
bootstrap_dba = dba;
/*
* PA2KA(identity) mapping for all frames.
*/
for (i = 0; i < config.memory_size/PAGE_SIZE; i++)
page_mapping_insert(PA2KA(i * PAGE_SIZE), i * PAGE_SIZE, PAGE_CACHEABLE, KA2PA(dba));
 
trap_register(14, page_fault);
write_cr3(KA2PA(dba));
}
else {
/*
* Application processors need to create their own view of the
* virtual address space. Because of that, each AP copies
* already-initialized paging information from the bootstrap
* processor and adjusts it to fulfill its needs.
*/
 
dba = frame_alloc(FRAME_KA | FRAME_PANIC);
memcpy((void *)dba, (void *)bootstrap_dba , PAGE_SIZE);
write_cr3(KA2PA(dba));
}
 
paging_on();
}
/kernel/trunk/arch/ia32/src/mm/tlb.c
0,0 → 1,42
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <mm/tlb.h>
#include <arch/mm/asid.h>
#include <arch/asm.h>
 
/** Invalidate all TLB entries
*
* Invalidate all TLB entries.
*
* @param asid This argument is ignored.
*/
void tlb_invalidate(asid_t asid)
{
write_cr3(read_cr3());
}
/kernel/trunk/arch/ia32/src/mm/memory_init.c
0,0 → 1,70
/*
* Copyright (C) 2005 Josef Cejka
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/boot/memmap.h>
#include <arch/mm/memory_init.h>
#include <arch/mm/page.h>
#include <print.h>
 
__u8 e820counter __attribute__ ((section ("BOOT_DATA"))) = 0xff;
struct e820memmap_ e820table[MEMMAP_E820_MAX_RECORDS] __attribute__ ((section ("BOOT_DATA"))) ;
 
size_t get_memory_size(void)
{
return e801memorysize*1024;
}
 
void memory_print_map(void)
{
__u8 i;
for (i=0;i<e820counter;i++) {
printf("E820 base: %Q size: %Q type: ", e820table[i].base_address, e820table[i].size);
switch (e820table[i].type) {
case MEMMAP_MEMORY_AVAILABLE:
printf("available memory\n");
break;
case MEMMAP_MEMORY_RESERVED:
printf("reserved memory\n");
break;
case MEMMAP_MEMORY_ACPI:
printf("ACPI table\n");
break;
case MEMMAP_MEMORY_NVS:
printf("NVS\n");
break;
case MEMMAP_MEMORY_UNUSABLE:
printf("unusable memory\n");
break;
default:
printf("undefined memory type\n");
}
}
 
}
 
/kernel/trunk/arch/ia32/src/mm/frame.c
0,0 → 1,61
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <mm/frame.h>
#include <arch/mm/frame.h>
#include <mm/vm.h>
#include <config.h>
#include <arch/boot/boot.h>
#include <arch/boot/memmap.h>
#include <panic.h>
 
size_t hardcoded_unmapped_ktext_size = 0;
size_t hardcoded_unmapped_kdata_size = 0;
 
void frame_arch_init(void)
{
zone_t *z;
__u8 i;
if (config.cpu_active == 1) {
for (i=0;i<e820counter;i++) {
if (e820table[i].type==MEMMAP_MEMORY_AVAILABLE) {
z = zone_create(e820table[i].base_address, e820table[i].size & ~(FRAME_SIZE-1), 0);
if (!z) {
panic("Cannot allocate zone (%dB).\n", e820table[i].size & ~(FRAME_SIZE-1));
}
zone_attach(z);
}
}
frame_not_free(0);
 
/* Reserve real mode bootstrap memory */
frame_region_not_free(BOOTSTRAP_OFFSET, BOOTSTRAP_OFFSET + hardcoded_unmapped_ktext_size + hardcoded_unmapped_kdata_size);
}
}
/kernel/trunk/arch/ia32/src/drivers/ega.c
0,0 → 1,118
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/ega.h>
#include <putchar.h>
#include <mm/page.h>
#include <arch/mm/page.h>
#include <synch/spinlock.h>
#include <arch/types.h>
#include <arch/asm.h>
#include <memstr.h>
 
/*
* The EGA driver.
* Simple and short. Function for displaying characters and "scrolling".
*/
 
static spinlock_t egalock;
static __u32 ega_cursor;
 
void ega_move_cursor(void);
 
void ega_init(void)
{
__u8 hi, lo;
 
page_mapping_insert(PA2KA(VIDEORAM), VIDEORAM, PAGE_NOT_CACHEABLE, 0);
outb(0x3d4,0xe);
hi = inb(0x3d5);
outb(0x3d4,0xf);
lo = inb(0x3d5);
ega_cursor = (hi<<8)|lo;
ega_putchar('\n');
}
 
static void ega_display_char(char ch)
{
__u8 *vram = (__u8 *) PA2KA(VIDEORAM);
vram[ega_cursor*2] = ch;
}
 
/*
* This function takes care of scrolling.
*/
static void ega_check_cursor(void)
{
if (ega_cursor < SCREEN)
return;
 
memcpy((void *)PA2KA(VIDEORAM), (void *)(PA2KA(VIDEORAM) + ROW*2), (SCREEN - ROW)*2);
memsetw(PA2KA(VIDEORAM) + (SCREEN - ROW)*2, ROW, 0x0720);
ega_cursor = ega_cursor - ROW;
}
 
void ega_putchar(const char ch)
{
ipl_t ipl;
 
ipl = interrupts_disable();
spinlock_lock(&egalock);
 
switch (ch) {
case '\n':
ega_cursor = (ega_cursor + ROW) - ega_cursor % ROW;
break;
case '\t':
ega_cursor = (ega_cursor + 8) - ega_cursor % 8;
break;
default:
ega_display_char(ch);
ega_cursor++;
break;
}
ega_check_cursor();
ega_move_cursor();
 
spinlock_unlock(&egalock);
interrupts_restore(ipl);
}
 
void ega_move_cursor(void)
{
outb(0x3d4,0xe);
outb(0x3d5,(ega_cursor>>8)&0xff);
outb(0x3d4,0xf);
outb(0x3d5,ega_cursor&0xff);
}
 
void putchar(const char ch)
{
ega_putchar(ch);
}
/kernel/trunk/arch/ia32/src/drivers/i8259.c
0,0 → 1,121
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/i8259.h>
#include <cpu.h>
#include <arch/types.h>
#include <arch/asm.h>
#include <arch.h>
#include <print.h>
 
/*
* This is the PIC driver.
* Programmable Interrupt Controller for UP systems.
*/
 
void i8259_init(void)
{
/* ICW1: this is ICW1, ICW4 to follow */
outb(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
 
/* ICW2: IRQ 0 maps to INT IRQBASE */
outb(PIC_PIC0PORT2, IVT_IRQBASE);
 
/* ICW3: pic1 using IRQ IRQ_PIC1 */
outb(PIC_PIC0PORT2, 1 << IRQ_PIC1);
 
/* ICW4: i8086 mode */
outb(PIC_PIC0PORT2, 1);
 
/* ICW1: ICW1, ICW4 to follow */
outb(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
 
/* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */
outb(PIC_PIC1PORT2, IVT_IRQBASE + 8);
 
/* ICW3: pic1 is known as IRQ_PIC1 */
outb(PIC_PIC1PORT2, IRQ_PIC1);
 
/* ICW4: i8086 mode */
outb(PIC_PIC1PORT2, 1);
 
/*
* Register interrupt handler for the PIC spurious interrupt.
*/
trap_register(VECTOR_PIC_SPUR, pic_spurious);
 
/*
* Set the enable/disable IRQs handlers.
* Set the End-of-Interrupt handler.
*/
enable_irqs_function = pic_enable_irqs;
disable_irqs_function = pic_disable_irqs;
eoi_function = pic_eoi;
 
pic_disable_irqs(0xffff); /* disable all irq's */
pic_enable_irqs(1<<IRQ_PIC1); /* but enable pic1 */
}
 
void pic_enable_irqs(__u16 irqmask)
{
__u8 x;
 
if (irqmask & 0xff) {
x = inb(PIC_PIC0PORT2);
outb(PIC_PIC0PORT2, x & (~(irqmask & 0xff)));
}
if (irqmask >> 8) {
x = inb(PIC_PIC1PORT2);
outb(PIC_PIC1PORT2, x & (~(irqmask >> 8)));
}
}
 
void pic_disable_irqs(__u16 irqmask)
{
__u8 x;
 
if (irqmask & 0xff) {
x = inb(PIC_PIC0PORT2);
outb(PIC_PIC0PORT2, x | (irqmask & 0xff));
}
if (irqmask >> 8) {
x = inb(PIC_PIC1PORT2);
outb(PIC_PIC1PORT2, x | (irqmask >> 8));
}
}
 
void pic_eoi(void)
{
outb(0x20,0x20);
outb(0xa0,0x20);
}
 
void pic_spurious(__u8 n, __native stack[])
{
printf("cpu%d: PIC spurious interrupt\n", CPU->id);
}
/kernel/trunk/arch/ia32/src/drivers/i8042.c
0,0 → 1,53
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/i8042.h>
#include <arch/i8259.h>
#include <arch/interrupt.h>
#include <cpu.h>
#include <arch/asm.h>
#include <arch.h>
#include <print.h>
 
/*
* i8042 processor driver.
*/
 
void i8042_init(void)
{
trap_register(VECTOR_KBD, i8042_interrupt);
}
 
void i8042_interrupt(__u8 n, __native stack[])
{
__u8 x;
 
trap_virtual_eoi();
x = inb(0x60);
printf("%d", CPU->id);;
}
/kernel/trunk/arch/ia32/src/drivers/i8254.c
0,0 → 1,129
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/types.h>
#include <time/clock.h>
#include <time/delay.h>
#include <arch/interrupt.h>
#include <arch/i8259.h>
#include <arch/i8254.h>
#include <cpu.h>
#include <config.h>
#include <arch/pm.h>
#include <arch/asm.h>
#include <arch/cpuid.h>
#include <arch.h>
#include <time/delay.h>
 
/*
* i8254 chip driver.
* Low level time functions.
*/
 
#define CLK_PORT1 0x40
#define CLK_PORT4 0x43
 
 
#define CLK_CONST 1193180
#define MAGIC_NUMBER 1194
 
void i8254_init(void)
{
i8254_normal_operation();
}
 
void i8254_normal_operation(void)
{
outb(CLK_PORT4, 0x36);
trap_virtual_disable_irqs(1<<IRQ_CLK);
outb(CLK_PORT1, (CLK_CONST/HZ) & 0xf);
outb(CLK_PORT1, (CLK_CONST/HZ) >> 8);
trap_virtual_enable_irqs(1<<IRQ_CLK);
trap_register(VECTOR_CLK, i8254_interrupt);
}
 
#define LOOPS 150000
#define SHIFT 11
void i8254_calibrate_delay_loop(void)
{
__u64 clk1, clk2;
__u32 t1, t2, o1, o2;
__u8 not_ok;
 
 
/*
* One-shot timer. Count-down from 0xffff at 1193180Hz
* MAGIC_NUMBER is the magic value for 1ms.
*/
outb(CLK_PORT4, 0x30);
outb(CLK_PORT1, 0xff);
outb(CLK_PORT1, 0xff);
 
do {
/* will read both status and count */
outb(CLK_PORT4, 0xc2);
not_ok = (inb(CLK_PORT1)>>6)&1;
t1 = inb(CLK_PORT1);
t1 |= inb(CLK_PORT1) << 8;
} while (not_ok);
 
asm_delay_loop(LOOPS);
 
outb(CLK_PORT4, 0xd2);
t2 = inb(CLK_PORT1);
t2 |= inb(CLK_PORT1) << 8;
 
/*
* We want to determine the overhead of the calibrating mechanism.
*/
outb(CLK_PORT4, 0xd2);
o1 = inb(CLK_PORT1);
o1 |= inb(CLK_PORT1) << 8;
 
asm_fake_loop(LOOPS);
 
outb(CLK_PORT4, 0xd2);
o2 = inb(CLK_PORT1);
o2 |= inb(CLK_PORT1) << 8;
 
CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0);
 
clk1 = rdtsc();
delay(1<<SHIFT);
clk2 = rdtsc();
CPU->frequency_mhz = (clk2-clk1)>>SHIFT;
 
return;
}
 
void i8254_interrupt(__u8 n, __native stack[])
{
trap_virtual_eoi();
clock();
}
/kernel/trunk/arch/ia32/src/boot/boot.S
0,0 → 1,254
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/boot/boot.h>
#include <arch/boot/memmapasm.h>
#include <arch/mm/page.h>
#include <arch/pm.h>
 
.section K_TEXT_START, "ax"
.global kernel_image_start
 
KTEXT=8
KDATA=16
 
.code16
#
# This is where we require any SPARTAN-kernel-compatible boot loader
# to pass control in real mode.
#
# Protected mode tables are statically initialised during compile
# time. So we can just load the respective table registers and
# switch to protected mode.
#
kernel_image_start:
cli
xorw %ax, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss # initialize stack segment register
movl $BOOTSTRAP_OFFSET - 0x400, %esp # initialize stack pointer
call memmap_arch_init
lgdt real_bootstrap_gdtr_boot # initialize Global Descriptor Table register
movl %cr0, %eax
orl $0x1, %eax
movl %eax, %cr0 # switch to protected mode
jmpl $KTEXT, $boot_image_start
.code32
.align 4
multiboot_header:
.long MULTIBOOT_HEADER_MAGIC
.long MULTIBOOT_HEADER_FLAGS
.long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) # checksum
.long multiboot_header + BOOT_OFFSET
.long unmapped_ktext_start + BOOT_OFFSET
.long 0
.long 0
.long multiboot_image_start + BOOT_OFFSET
boot_image_start:
movw $KDATA, %ax
movw %ax, %es
movw %ax, %gs
movw %ax, %fs
movw %ax, %ds # kernel data + stack
movw %ax, %ss
movb $0xd1, %al # enable A20 using i8042 controller
outb %al, $0x64
movb $0xdf, %al
outb %al, $0x60
movl $BOOTSTRAP_OFFSET, %esi
movl $BOOTSTRAP_OFFSET + BOOT_OFFSET, %edi
movl $_hardcoded_kernel_size, %ecx
cld
rep movsb
call map_kernel # map kernel and turn paging on
call main_bsp # never returns
 
cli
hlt
multiboot_image_start:
movl $BOOTSTRAP_OFFSET - 0x400, %esp # initialize stack pointer
lgdt protected_bootstrap_gdtr - 0x80000000 # initialize Global Descriptor Table register
 
movw $KDATA, %cx
movw %cx, %es
movw %cx, %gs
movw %cx, %fs
movw %cx, %ds # kernel data + stack
movw %cx, %ss
jmpl $KTEXT, $multiboot_meeting_point + BOOT_OFFSET
multiboot_meeting_point:
pushl %ebx # save parameters from GRUB
pushl %eax
movl $BOOTSTRAP_OFFSET + BOOT_OFFSET, %esi
movl $BOOTSTRAP_OFFSET, %edi
movl $_hardcoded_unmapped_size, %ecx
cld
rep movsb
call map_kernel # map kernel and turn paging on
popl %eax
popl %ebx
cmpl $MULTIBOOT_LOADER_MAGIC, %eax # compare GRUB signature
je valid_boot
xorl %ecx, %ecx # no memory size or map available
movl %ecx, e801memorysize
movl %ecx, e820counter
jmp invalid_boot
valid_boot:
movl (%ebx), %eax # ebx = physical address of struct multiboot_info
bt $0, %eax # mbi->flags[0] (mem_lower, mem_upper valid)
jc mem_valid
xorl %ecx, %ecx
jmp mem_invalid
mem_valid:
movl 4(%ebx), %ecx # mbi->mem_lower
addl 8(%ebx), %ecx # mbi->mem_upper
mem_invalid:
movl %ecx, e801memorysize
bt $6, %eax # mbi->flags[6] (mmap_length, mmap_addr valid)
jc mmap_valid
xorl %edx, %edx
jmp mmap_invalid
mmap_valid:
movl 44(%ebx), %ecx # mbi->mmap_length
movl 48(%ebx), %esi # mbi->mmap_addr
movl $e820table, %edi
xorl %edx, %edx
mmap_loop:
cmpl $0, %ecx
jle mmap_end
movl 4(%esi), %eax # mmap->base_addr_low
movl %eax, (%edi)
movl 8(%esi), %eax # mmap->base_addr_high
movl %eax, 4(%edi)
movl 12(%esi), %eax # mmap->length_low
movl %eax, 8(%edi)
movl 16(%esi), %eax # mmap->length_high
movl %eax, 12(%edi)
movl 20(%esi), %eax # mmap->type
movl %eax, 16(%edi)
movl (%esi), %eax # mmap->size
addl $0x4, %eax
addl %eax, %esi
subl %eax, %ecx
addl $MEMMAP_E820_RECORD_SIZE, %edi
incl %edx
jmp mmap_loop
mmap_end:
mmap_invalid:
movl %edx, e820counter
invalid_boot:
call main_bsp - BOOT_OFFSET # never returns
 
cli
hlt
 
.global map_kernel
map_kernel:
#
# Here we setup mapping for both the unmapped and mapped sections of the kernel.
# For simplicity, we map the entire 4G space.
#
movl %cr4, %ecx
orl $(1<<4), %ecx
movl %ecx, %cr4 # turn PSE on
movl $(page_directory+0), %esi
movl $(page_directory+2048), %edi
xorl %ecx, %ecx
xorl %ebx, %ebx
0:
movl $((1<<7)|(1<<0)), %eax
orl %ebx, %eax
movl %eax, (%esi,%ecx,4) # mapping 0x00000000+%ecx*4M => 0x00000000+%ecx*4M
movl %eax, (%edi,%ecx,4) # mapping 0x80000000+%ecx*4M => 0x00000000+%ecx*4M
addl $(4*1024*1024), %ebx
 
incl %ecx
cmpl $512, %ecx
jl 0b
 
movl %esi, %cr3
# turn paging on
movl %cr0, %ebx
orl $(1<<31), %ebx
movl %ebx, %cr0
ret
 
 
.section K_DATA_START, "aw", @progbits
 
.align 4096
page_directory:
.space 4096, 0
 
.global real_bootstrap_gdtr_boot
real_bootstrap_gdtr_boot:
.word selector(GDT_ITEMS)
.long KA2PA(gdt)-BOOT_OFFSET
 
/kernel/trunk/arch/ia32/src/boot/memmap.S
0,0 → 1,115
/*
* Copyright (C) 2005 Josef Cejka
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
#include <arch/boot/memmapasm.h>
 
E820_SMAP = 0x534d4150
 
.global memmap_arch_init
.global e801memorysize
 
.code16
.section K_TEXT_START_2, "ax"
 
memmap_arch_init:
e820begin:
xorl %ebx,%ebx # during first call, ebx must be 0
movw $e820table_boot,%di
movb $MEMMAP_E820_MAX_RECORDS,e820counter_boot
e820loop:
movl $E820_SMAP,%edx # control sequence "SMAP"
 
movl $0x0000e820,%eax # service
movl $MEMMAP_E820_RECORD_SIZE,%ecx
int $0x15
jc e820err
cmpl $E820_SMAP,%eax # verifying BIOS
jne e820err
 
cmpl $MEMMAP_E820_RECORD_SIZE,%ecx
jne e820err # bad record size - bug in bios
movw %di,%ax # next record
addw $MEMMAP_E820_RECORD_SIZE,%ax
movw %ax,%di
decb e820counter_boot # buffer is full
jz e820end
testl %ebx,%ebx
jnz e820loop
e820end:
movb $MEMMAP_E820_MAX_RECORDS,%al
subb e820counter_boot,%al
movb %al,e820counter_boot # store # of valid entries in e820counter
 
jmp e801begin
 
e820err:
movb $0,e820counter_boot
 
# method e801 - get size of memory
 
e801begin:
xorw %dx,%dx
xorw %cx,%cx
xorw %bx,%bx
movw $0xe801,%ax
stc
int $0x15
jc e801end
# fix problem with some BIOSes which use ax:bx rather than cx:dx
testw %cx,%cx
jnz e801cxdx
testw %dx,%dx
jnz e801cxdx
 
movw %ax,%cx
movw %bx,%dx
e801cxdx:
andl $0xffff,%edx
shll $6,%edx
andl $0xffff,%ecx
addl %ecx,%edx
addl $0x0400,%edx # add lower 1 MB - it's not included by e801 method
movl %edx,e801memorysize
e801end:
ret
 
 
.section K_DATA_START, "aw", @progbits
 
#memory size in 1 kb chunks
e801memorysize:
.long 0
/kernel/trunk/arch/ia32/src/ia32.c
0,0 → 1,94
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch.h>
 
#include <arch/types.h>
#include <typedefs.h>
 
#include <arch/pm.h>
 
#include <arch/ega.h>
#include <arch/i8042.h>
#include <arch/i8254.h>
#include <arch/i8259.h>
 
#include <arch/context.h>
 
#include <config.h>
 
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <genarch/acpi/acpi.h>
 
#include <arch/bios/bios.h>
 
#include <arch/mm/memory_init.h>
 
void arch_pre_mm_init(void)
{
pm_init();
 
if (config.cpu_active == 1) {
bios_init();
i8042_init(); /* keyboard controller */
i8259_init(); /* PIC */
i8254_init(); /* hard clock */
trap_register(VECTOR_SYSCALL, syscall);
#ifdef CONFIG_SMP
trap_register(VECTOR_TLB_SHOOTDOWN_IPI, tlb_shootdown_ipi);
trap_register(VECTOR_WAKEUP_IPI, wakeup_ipi);
#endif /* CONFIG_SMP */
}
}
 
void arch_post_mm_init(void)
{
if (config.cpu_active == 1) {
ega_init(); /* video */
}
}
 
void arch_late_init(void)
{
if (config.cpu_active == 1) {
memory_print_map();
#ifdef CONFIG_SMP
acpi_init();
#endif /* CONFIG_SMP */
}
}
 
void calibrate_delay_loop(void)
{
i8254_calibrate_delay_loop();
i8254_normal_operation();
}
/kernel/trunk/arch/ia32/src/interrupt.c
0,0 → 1,169
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/interrupt.h>
#include <print.h>
#include <debug.h>
#include <panic.h>
#include <arch/i8259.h>
#include <func.h>
#include <cpu.h>
#include <arch/asm.h>
#include <mm/tlb.h>
#include <arch.h>
#include <symtab.h>
#include <proc/thread.h>
 
/*
* Interrupt and exception dispatching.
*/
 
static iroutine ivt[IVT_ITEMS];
 
void (* disable_irqs_function)(__u16 irqmask) = NULL;
void (* enable_irqs_function)(__u16 irqmask) = NULL;
void (* eoi_function)(void) = NULL;
 
#define PRINT_INFO_ERRCODE(x) { \
char *symbol = get_symtab_entry(stack[1]); \
if (!symbol) \
symbol = ""; \
printf("----------------EXCEPTION OCCURED----------------\n"); \
printf("%%eip: %X (%s)\n",x[1],symbol); \
printf("ERROR_WORD=%X\n", x[0]); \
printf("%%cs=%X,flags=%X\n", x[2], x[3]); \
printf("%%eax=%X, %%ebx=%X, %%ecx=%X, %%edx=%X\n",\
x[-2],x[-5],x[-3],x[-4]); \
printf("%%esi=%X, %%edi=%X, %%ebp=%X, %%esp=%X\n",\
x[-8],x[-9],x[-1],x); \
printf("stack: %X, %X, %X, %X\n", x[4], x[5], x[6], x[7]); \
printf(" %X, %X, %X, %X\n", x[8], x[9], x[10], x[11]); \
}
 
iroutine trap_register(__u8 n, iroutine f)
{
ASSERT(n < IVT_ITEMS);
iroutine old;
old = ivt[n];
ivt[n] = f;
return old;
}
 
/*
* Called directly from the assembler code.
* CPU is interrupts_disable()'d.
*/
void trap_dispatcher(__u8 n, __native stack[])
{
ASSERT(n < IVT_ITEMS);
ivt[n](n, stack);
}
 
void null_interrupt(__u8 n, __native stack[])
{
printf("int %d: null_interrupt\n", n);
printf("stack: %L, %L, %L, %L\n", stack[0], stack[1], stack[2], stack[3]);
panic("unserviced interrupt\n");
}
 
void gp_fault(__u8 n, __native stack[])
{
PRINT_INFO_ERRCODE(stack);
panic("general protection fault\n");
}
 
void ss_fault(__u8 n, __native stack[])
{
PRINT_INFO_ERRCODE(stack);
panic("stack fault\n");
}
 
 
void nm_fault(__u8 n, __native stack[])
{
#ifdef CONFIG_FPU_LAZY
scheduler_fpu_lazy_request();
#else
panic("fpu fault");
#endif
}
 
 
 
void page_fault(__u8 n, __native stack[])
{
PRINT_INFO_ERRCODE(stack);
printf("page fault address: %X\n", read_cr2());
panic("page fault\n");
}
 
void syscall(__u8 n, __native stack[])
{
printf("cpu%d: syscall\n", CPU->id);
thread_usleep(1000);
}
 
void tlb_shootdown_ipi(__u8 n, __native stack[])
{
trap_virtual_eoi();
tlb_shootdown_ipi_recv();
}
 
void wakeup_ipi(__u8 n, __native stack[])
{
trap_virtual_eoi();
}
 
void trap_virtual_enable_irqs(__u16 irqmask)
{
if (enable_irqs_function)
enable_irqs_function(irqmask);
else
panic("no enable_irqs_function\n");
}
 
void trap_virtual_disable_irqs(__u16 irqmask)
{
if (disable_irqs_function)
disable_irqs_function(irqmask);
else
panic("no disable_irqs_function\n");
}
 
void trap_virtual_eoi(void)
{
if (eoi_function)
eoi_function();
else
panic("no eoi_function\n");
 
}
/kernel/trunk/arch/ia32/src/atomic.S
0,0 → 1,60
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
.text
 
#ifdef CONFIG_SMP
 
.global spinlock_arch
 
#
# This is a bus-and-hyperthreading-friendly implementation of spinlock
#
spinlock_arch:
pushl %eax
pushl %ebx
movl 12(%esp),%ebx
 
0:
#ifdef CONFIG_HT
pause # Pentium 4's with HT love this instruction
#endif
movl (%ebx),%eax
testl %eax,%eax
jnz 0b # lightweight looping while it is locked
incl %eax
xchgl %eax,(%ebx) # now use the atomic operation
testl %eax,%eax
jnz 0b
 
popl %ebx
popl %eax
ret
#endif
/kernel/trunk/arch/ia32/src/cpu/cpu.c
0,0 → 1,134
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <arch/pm.h>
 
#include <arch.h>
#include <arch/types.h>
#include <print.h>
#include <typedefs.h>
#include <fpu_context.h>
 
#include <arch/smp/apic.h>
 
/*
* Identification of CPUs.
* Contains only non-MP-Specification specific SMP code.
*/
#define AMD_CPUID_EBX 0x68747541
#define AMD_CPUID_ECX 0x444d4163
#define AMD_CPUID_EDX 0x69746e65
 
#define INTEL_CPUID_EBX 0x756e6547
#define INTEL_CPUID_ECX 0x6c65746e
#define INTEL_CPUID_EDX 0x49656e69
 
 
enum vendor {
VendorUnknown=0,
VendorAMD,
VendorIntel
};
 
static char *vendor_str[] = {
"Unknown Vendor",
"AuthenticAMD",
"GenuineIntel"
};
 
void fpu_disable(void)
{
__asm__ volatile (
"mov %%cr0,%%eax;"
"or $8,%%eax;"
"mov %%eax,%%cr0;"
:
:
:"%eax"
);
}
 
void fpu_enable(void)
{
__asm__ volatile (
"mov %%cr0,%%eax;"
"and $0xffFFffF7,%%eax;"
"mov %%eax,%%cr0;"
:
:
:"%eax"
);
}
 
 
 
 
void cpu_arch_init(void)
{
CPU->arch.tss = tss_p;
CPU->fpu_owner=NULL;
}
 
 
void cpu_identify(void)
{
cpu_info_t info;
 
CPU->arch.vendor = VendorUnknown;
if (has_cpuid()) {
cpuid(0, &info);
 
/*
* Check for AMD processor.
*/
if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
CPU->arch.vendor = VendorAMD;
}
 
/*
* Check for Intel processor.
*/
if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
CPU->arch.vendor = VendorIntel;
}
cpuid(1, &info);
CPU->arch.family = (info.cpuid_eax>>8)&0xf;
CPU->arch.model = (info.cpuid_eax>>4)&0xf;
CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
}
}
 
void cpu_print_report(cpu_t* m)
{
printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
m->frequency_mhz);
}
/kernel/trunk/arch/ia32/src/context.s
0,0 → 1,72
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
.text
 
.global context_save_arch
.global context_restore_arch
 
 
## Save current CPU context
#
# Save CPU context to the context_t variable
# pointed by the 1st argument. Returns 1 in EAX.
#
context_save_arch:
movl 0(%esp),%eax # the caller's return %eip
movl 4(%esp),%edx # address of the kernel_context variable to save context to
 
movl %esp,0(%edx) # %esp -> ctx->sp
movl %eax,4(%edx) # %eip -> ctx->pc
movl %ebx,8(%edx) # %ebx -> ctx->ebx
movl %esi,12(%edx) # %esi -> ctx->esi
movl %edi,16(%edx) # %edi -> ctx->edi
movl %ebp,20(%edx) # %ebp -> ctx->ebp
 
xorl %eax,%eax # context_save returns 1
incl %eax
ret
 
 
## Restore saved CPU context
#
# Restore CPU context from context_t variable
# pointed by the 1st argument. Returns 0 in EAX.
#
context_restore_arch:
movl 4(%esp),%eax # address of the kernel_context variable to restore context from
movl 0(%eax),%esp # ctx->sp -> %esp
movl 4(%eax),%edx # ctx->pc -> %edx
movl 8(%eax),%ebx # ctx->ebx -> %ebx
movl 12(%eax),%esi # ctx->esi -> %esi
movl 16(%eax),%edi # ctx->edi -> %edi
movl 20(%eax),%ebp # ctx->ebp -> %ebp
 
movl %edx,0(%esp) # ctx->pc -> saver's return %eip
xorl %eax,%eax # context_restore returns 0
ret
/kernel/trunk/arch/ia32/src/userspace.c
0,0 → 1,68
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <userspace.h>
#include <arch/pm.h>
#include <arch/types.h>
#include <arch.h>
#include <proc/thread.h>
#include <mm/vm.h>
 
 
/** Enter userspace
*
* Change CPU protection level to 3, enter userspace.
*
*/
void userspace(void)
{
ipl_t ipl;
ipl = interrupts_disable();
 
__asm__ volatile (
/* CLNT */
"pushfl;"
"pop %%eax;"
"and $0xFFFFBFFF,%%eax;"
"push %%eax;"
"popfl;"
 
"pushl %0\n"
"pushl %1\n"
"pushl %2\n"
"pushl %3\n"
"pushl %4\n"
"iret"
:
: "i" (selector(UDATA_DES) | PL_USER), "r" (USTACK_ADDRESS+(THREAD_STACK_SIZE)), "r" (ipl), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)
: "eax");
/* Unreachable */
for(;;);
}
/kernel/trunk/arch/ia32/src/asm.S
0,0 → 1,173
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
## very low and hardware-level functions
 
# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
# and 1 means interrupt with error word
#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
 
.text
 
.global paging_on
.global enable_l_apic_in_msr
.global interrupt_handlers
 
## Turn paging on
#
# Enable paging and write-back caching in CR0.
#
paging_on:
movl %cr0,%edx
orl $(1<<31),%edx # paging on
andl $~((1<<30)|(1<<29)),%edx # clear Cache Disable and not Write Though
movl %edx,%cr0
jmp 0f
0:
ret
 
 
## Enable local APIC
#
# Enable local APIC in MSR.
#
enable_l_apic_in_msr:
push %eax
 
movl $0x1b, %ecx
rdmsr
orl $(1<<11),%eax
orl $(0xfee00000),%eax
wrmsr
 
pop %eax
ret
 
 
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers setup data segment registers
# and call trap_dispatcher().
#
.macro handler i n
push %ebp
movl %esp,%ebp
pusha
 
push %ds
push %es
 
# we must fill the data segment registers
movw $16,%ax
movw %ax,%ds
movw %ax,%es
 
movl $(\i),%edi
pushl %ebp
addl $4,(%esp)
pushl %edi
call trap_dispatcher
addl $8,%esp
 
pop %es
pop %ds
 
 
# CLNT
pushfl
pop %eax
and $0xFFFFBFFF,%eax
push %eax
popfl
 
 
# Test if this is interrupt with error word or not
mov $\i,%cl
movl $1,%eax
test $0xe0,%cl
jnz 0f
and $0x1f,%cl
shl %cl,%eax
and $ERROR_WORD_INTERRUPT_LIST,%eax
jz 0f
 
 
# Return with error word
popa
pop %ebp
add $4,%esp # Skip error word
iret
 
0:
# Return with no error word
popa
pop %ebp
iret
 
.if (\n-\i)-1
handler "(\i+1)",\n
.endif
.endm
 
# keep in sync with pm.h !!!
IDT_ITEMS=64
interrupt_handlers:
h_start:
handler 0 64
# handler 64 128
# handler 128 192
# handler 192 256
h_end:
 
 
# THIS IS USERSPACE CODE
.global utext
utext:
xor %ax,%ax
mov %ax,%ds
mov %ax,%es
mov %ax,%fs
mov %ax,%gs
0:
int $48
jmp 0b
# not reached
utext_end:
 
.data
.global utext_size
utext_size:
.long utext_end - utext
 
.global interrupt_handler_size
 
interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
/kernel/trunk/arch/ia32/src/delay.s
0,0 → 1,50
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#
# Micro second delay loop functions.
#
 
.text
 
.global asm_delay_loop
.global asm_fake_loop
 
asm_delay_loop:
movl 4(%esp),%ecx # move argument to %ecx
0: lahf
dec %ecx
jnz 0b
ret
 
asm_fake_loop:
movl 4(%esp),%ecx # move argument to %ecx
0: lahf
dec %ecx
jz 0b
ret
/kernel/trunk/arch/ia32/src/pm.c
0,0 → 1,214
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/pm.h>
#include <config.h>
#include <arch/types.h>
#include <typedefs.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <arch/context.h>
#include <panic.h>
#include <arch/mm/page.h>
#include <mm/heap.h>
#include <memstr.h>
#include <arch/boot/boot.h>
 
/*
* Early ia32 configuration functions and data structures.
*/
 
/*
* We have no use for segmentation so we set up flat mode. In this
* mode, we use, for each privilege level, two segments spanning the
* whole memory. One is for code and one is for data.
*/
struct descriptor gdt[GDT_ITEMS] = {
/* NULL descriptor */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
/* KTEXT descriptor */
{ 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
/* KDATA descriptor */
{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
/* UTEXT descriptor */
{ 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
/* UDATA descriptor */
{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
/* TSS descriptor - set up will be completed later */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
};
 
static struct idescriptor idt[IDT_ITEMS];
 
static struct tss tss;
 
struct tss *tss_p = NULL;
 
/* gdtr is changed by kmp before next CPU is initialized */
struct ptr_16_32 protected_bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
struct ptr_16_32 gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
 
void gdt_setbase(struct descriptor *d, __address base)
{
d->base_0_15 = base & 0xffff;
d->base_16_23 = ((base) >> 16) & 0xff;
d->base_24_31 = ((base) >> 24) & 0xff;
}
 
void gdt_setlimit(struct descriptor *d, __u32 limit)
{
d->limit_0_15 = limit & 0xffff;
d->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(struct idescriptor *d, __address offset)
{
/*
* Offset is a linear address.
*/
d->offset_0_15 = offset & 0xffff;
d->offset_16_31 = offset >> 16;
}
 
void tss_initialize(struct tss *t)
{
memsetb((__address) t, sizeof(struct tss), 0);
}
 
/*
* This function takes care of proper setup of IDT and IDTR.
*/
void idt_init(void)
{
struct idescriptor *d;
int i;
 
for (i = 0; i < IDT_ITEMS; i++) {
d = &idt[i];
 
d->unused = 0;
d->selector = selector(KTEXT_DES);
 
d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */
 
if (i == VECTOR_SYSCALL) {
/*
* The syscall interrupt gate must be calleable from userland.
*/
d->access |= DPL_USER;
}
idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
trap_register(i, null_interrupt);
}
trap_register(13, gp_fault);
trap_register( 7, nm_fault);
trap_register(12, ss_fault);
}
 
 
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
static void clean_IOPL_NT_flags(void)
{
asm
(
"pushfl;"
"pop %%eax;"
"and $0xffff8fff,%%eax;"
"push %%eax;"
"popfl;"
:
:
:"%eax"
);
}
 
/* Clean AM(18) flag in CR0 register */
static void clean_AM_flag(void)
{
asm
(
"mov %%cr0,%%eax;"
"and $0xFFFBFFFF,%%eax;"
"mov %%eax,%%cr0;"
:
:
:"%eax"
);
}
 
void pm_init(void)
{
struct descriptor *gdt_p = (struct descriptor *) gdtr.base;
struct ptr_16_32 idtr;
 
/*
* Update addresses in GDT and IDT to their virtual counterparts.
*/
idtr.limit = sizeof(idt);
idtr.base = (__address) idt;
__asm__ volatile ("lgdt %0\n" : : "m" (gdtr));
__asm__ volatile ("lidt %0\n" : : "m" (idtr));
/*
* Each CPU has its private GDT and TSS.
* All CPUs share one IDT.
*/
 
if (config.cpu_active == 1) {
idt_init();
/*
* NOTE: bootstrap CPU has statically allocated TSS, because
* the heap hasn't been initialized so far.
*/
tss_p = &tss;
}
else {
tss_p = (struct tss *) malloc(sizeof(struct tss));
if (!tss_p)
panic("could not allocate TSS\n");
}
 
tss_initialize(tss_p);
gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
gdt_p[TSS_DES].special = 1;
gdt_p[TSS_DES].granularity = 1;
gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
 
/*
* As of this moment, the current CPU has its own GDT pointing
* to its own TSS. We just need to load the TR register.
*/
__asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */
clean_AM_flag(); /* Disable alignment check */
}
/kernel/trunk/arch/ia32/src/fpu_context.c
0,0 → 1,56
/*
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
 
#include <fpu_context.h>
#include <arch.h>
#include <cpu.h>
 
void fpu_context_save(fpu_context_t *fctx)
{
__asm__ volatile (
"fnsave %0"
: "=m"(*fctx)
);
}
 
 
void fpu_context_restore(fpu_context_t *fctx)
{
__asm__ volatile (
"frstor %0"
: "=m"(*fctx)
);
}
 
void fpu_init(void)
{
__asm__ volatile (
"fninit;"
);
}
/kernel/trunk/arch/ia32/src/fmath.c
0,0 → 1,146
/*
* Copyright (C) 2005 Josef Cejka
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/fmath.h>
#include <print.h>
 
#define FMATH_MANTISA_MASK ( 0x000fffffffffffffLL )
#define FMATH_NAN ( 0x0001000000000001LL )
signed short fmath_get_binary_exponent(double num)
{
fmath_ld_union_t fmath_ld_union;
fmath_ld_union.bf = num;
return (signed short)((((fmath_ld_union.ldd[7])&0x7f)<<4) + (((fmath_ld_union.ldd[6])&0xf0)>>4)) -FMATH_EXPONENT_BIAS; /* exponent is 11 bits lenght, so sevent bits is in 8th byte and 4 bits in 7th */
}
 
double fmath_get_decimal_exponent(double num)
{
double value;
/* log10(2)*log2(x) => log10(x) */
__asm__ __volatile__ ( \
"fldlg2 #load log10(2) \n\t" \
"fxch %%st(1) \n\t" \
"fyl2x #count st(0)*log2(st(1))->st(1); pop st(0) \n\t" \
: "=t" (value) : "0"(num) );
return value;
}
 
__u64 fmath_get_binary_mantisa(double num)
{
union { __u64 _u; double _d;} un = { _d : num };
un._u=un._u &(FMATH_MANTISA_MASK); /* mask 52 bits of mantisa*/
return un._u;
}
 
double fmath_fint(double num, double *intp)
{
fmath_ld_union_t fmath_ld_union_num;
fmath_ld_union_t fmath_ld_union_int;
signed short exp;
__u64 mask,mantisa;
int i;
exp=fmath_get_binary_exponent(num);
if (exp<0) {
*intp = 0.0;
return num;
}
 
if (exp>51) {
*intp=num;
num=0.0;
return num;
}
fmath_ld_union_num.bf = num;
mask = FMATH_MANTISA_MASK>>exp;
//mantisa = (fmath_get-binary_mantisa(num))&(~mask);
for (i=0;i<7;i++) {
/* Ugly construction for obtain sign, exponent and integer part from num */
fmath_ld_union_int.ldd[i]=fmath_ld_union_num.ldd[i]&(((~mask)>>(i*8))&0xff);
}
fmath_ld_union_int.ldd[6]|=((fmath_ld_union_num.ldd[6])&(0xf0));
fmath_ld_union_int.ldd[7]=fmath_ld_union_num.ldd[7];
*intp=fmath_ld_union_int.bf;
return fmath_ld_union_num.bf-fmath_ld_union_int.bf;
};
 
double fmath_dpow(double base, double exponent)
{
double value=1.0;
if (base<=0.0) return base;
//2^(x*log2(10)) = 2^y = 10^x
__asm__ __volatile__ ( \
"fyl2x # ST(1):=ST(1)*log2(ST(0)), pop st(0) \n\t " \
"fld %%st(0) \n\t" \
"frndint \n\t" \
"fxch %%st(1) \n\t" \
"fsub %%st(1),%%st(0) \n\t" \
"f2xm1 # ST := 2^ST -1\n\t" \
"fld1 \n\t" \
"faddp %%st(0),%%st(1) \n\t" \
"fscale #ST:=ST*2^(ST(1))\n\t" \
"fstp %%st(1) \n\t" \
"" : "=t" (value) : "0" (base), "u" (exponent) );
return value;
}
 
int fmath_is_nan(double num)
{
__u16 exp;
fmath_ld_union_t fmath_ld_union;
fmath_ld_union.bf = num;
exp=(((fmath_ld_union.ldd[7])&0x7f)<<4) + (((fmath_ld_union.ldd[6])&0xf0)>>4); /* exponent is 11 bits lenght, so sevent bits is in 8th byte and 4 bits in 7th */
 
if (exp!=0x07ff) return 0;
if (fmath_get_binary_mantisa(num)>=FMATH_NAN) return 1;
return 0;
}
 
int fmath_is_infinity(double num)
{
__u16 exp;
fmath_ld_union_t fmath_ld_union;
fmath_ld_union.bf = num;
exp=(((fmath_ld_union.ldd[7])&0x7f)<<4) + (((fmath_ld_union.ldd[6])&0xf0)>>4); /* exponent is 11 bits lenght, so sevent bits is in 8th byte and 4 bits in 7th */
 
if (exp!=0x07ff) return 0;
if (fmath_get_binary_mantisa(num)==0x0) return 1;
return 0;
}
/kernel/trunk/arch/ia32/src/proc/scheduler.c
0,0 → 1,39
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <proc/scheduler.h>
#include <cpu.h>
#include <proc/thread.h>
#include <arch.h>
#include <arch/context.h> /* SP_DELTA */
 
void before_thread_runs_arch(void)
{
CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
CPU->arch.tss->ss0 = selector(KDATA_DES);
}
/kernel/trunk/arch/ia32/src/debug/panic.s
0,0 → 1,34
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
.text
.global panic_printf
 
panic_printf:
movl $halt,(%esp) # fake stack to make printf return to halt
jmp printf
/kernel/trunk/arch/ia32/src/bios/bios.c
0,0 → 1,38
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#include <arch/bios/bios.h>
#include <arch/types.h>
 
__address ebda = 0;
 
void bios_init(void)
{
/* Copy the EBDA address out from BIOS Data Area */
ebda = *((__u16 *) BIOS_EBDA_PTR) * 0x10;
}