56,8 → 56,8 |
* Interrupt and exception dispatching. |
*/ |
|
void (* disable_irqs_function)(__u16 irqmask) = NULL; |
void (* enable_irqs_function)(__u16 irqmask) = NULL; |
void (* disable_irqs_function)(uint16_t irqmask) = NULL; |
void (* enable_irqs_function)(uint16_t irqmask) = NULL; |
void (* eoi_function)(void) = NULL; |
|
void PRINT_INFO_ERRCODE(istate_t *istate) |
129,7 → 129,7 |
|
void simd_fp_exception(int n, istate_t *istate) |
{ |
__u32 mxcsr; |
uint32_t mxcsr; |
asm |
( |
"stmxcsr %0;\n" |
136,10 → 136,10 |
:"=m"(mxcsr) |
); |
fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx", |
(__native)mxcsr); |
(unative_t)mxcsr); |
|
PRINT_INFO_ERRCODE(istate); |
printf("MXCSR: %#zx\n",(__native)(mxcsr)); |
printf("MXCSR: %#zx\n",(unative_t)(mxcsr)); |
panic("SIMD FP exception(19)\n"); |
} |
|
164,7 → 164,7 |
tlb_shootdown_ipi_recv(); |
} |
|
void trap_virtual_enable_irqs(__u16 irqmask) |
void trap_virtual_enable_irqs(uint16_t irqmask) |
{ |
if (enable_irqs_function) |
enable_irqs_function(irqmask); |
172,7 → 172,7 |
panic("no enable_irqs_function\n"); |
} |
|
void trap_virtual_disable_irqs(__u16 irqmask) |
void trap_virtual_disable_irqs(uint16_t irqmask) |
{ |
if (disable_irqs_function) |
disable_irqs_function(irqmask); |
197,7 → 197,7 |
|
|
/* Reregister irq to be IPC-ready */ |
void irq_ipc_bind_arch(__native irq) |
void irq_ipc_bind_arch(unative_t irq) |
{ |
if (irq == IRQ_CLK) |
return; |