/kernel/trunk/arch/ia32/include/interrupt.h |
---|
69,24 → 69,24 |
#define VECTOR_DEBUG_IPI (IVT_FREEBASE+2) |
struct istate { |
__u32 eax; |
__u32 ecx; |
__u32 edx; |
__u32 esi; |
__u32 edi; |
__u32 ebp; |
__u32 ebx; |
uint32_t eax; |
uint32_t ecx; |
uint32_t edx; |
uint32_t esi; |
uint32_t edi; |
uint32_t ebp; |
uint32_t ebx; |
__u32 gs; |
__u32 fs; |
__u32 es; |
__u32 ds; |
uint32_t gs; |
uint32_t fs; |
uint32_t es; |
uint32_t ds; |
__u32 error_word; |
__u32 eip; |
__u32 cs; |
__u32 eflags; |
__u32 stack[]; |
uint32_t error_word; |
uint32_t eip; |
uint32_t cs; |
uint32_t eflags; |
uint32_t stack[]; |
}; |
/** Return true if exception happened while in userspace */ |
95,18 → 95,18 |
return !(istate->eip & 0x80000000); |
} |
static inline void istate_set_retaddr(istate_t *istate, __address retaddr) |
static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) |
{ |
istate->eip = retaddr; |
} |
static inline __native istate_get_pc(istate_t *istate) |
static inline unative_t istate_get_pc(istate_t *istate) |
{ |
return istate->eip; |
} |
extern void (* disable_irqs_function)(__u16 irqmask); |
extern void (* enable_irqs_function)(__u16 irqmask); |
extern void (* disable_irqs_function)(uint16_t irqmask); |
extern void (* enable_irqs_function)(uint16_t irqmask); |
extern void (* eoi_function)(void); |
extern void PRINT_INFO_ERRCODE(istate_t *istate); |
118,8 → 118,8 |
extern void syscall(int n, istate_t *istate); |
extern void tlb_shootdown_ipi(int n, istate_t *istate); |
extern void trap_virtual_enable_irqs(__u16 irqmask); |
extern void trap_virtual_disable_irqs(__u16 irqmask); |
extern void trap_virtual_enable_irqs(uint16_t irqmask); |
extern void trap_virtual_disable_irqs(uint16_t irqmask); |
extern void trap_virtual_eoi(void); |
#endif |
/kernel/trunk/arch/ia32/include/fpu_context.h |
---|
45,7 → 45,7 |
struct fpu_context { |
__u8 fpu[512]; /* FXSAVE & FXRSTOR storage area */ |
uint8_t fpu[512]; /* FXSAVE & FXRSTOR storage area */ |
}; |
/kernel/trunk/arch/ia32/include/byteorder.h |
---|
36,8 → 36,8 |
#define __ia32_BYTEORDER_H__ |
/* IA-32 is little-endian */ |
#define __native_le2host(n) (n) |
#define __u64_le2host(n) (n) |
#define unative_t_le2host(n) (n) |
#define uint64_t_le2host(n) (n) |
#endif |
/kernel/trunk/arch/ia32/include/cpuid.h |
---|
38,10 → 38,10 |
#include <arch/types.h> |
struct cpu_info { |
__u32 cpuid_eax; |
__u32 cpuid_ebx; |
__u32 cpuid_ecx; |
__u32 cpuid_edx; |
uint32_t cpuid_eax; |
uint32_t cpuid_ebx; |
uint32_t cpuid_ecx; |
uint32_t cpuid_edx; |
} __attribute__ ((packed)); |
struct __cpuid_extended_feature_info { |
52,7 → 52,7 |
typedef union cpuid_extended_feature_info |
{ |
struct __cpuid_extended_feature_info bits; |
__u32 word; |
uint32_t word; |
}cpuid_extended_feature_info; |
68,13 → 68,13 |
typedef union cpuid_feature_info |
{ |
struct __cpuid_feature_info bits; |
__u32 word ; |
uint32_t word ; |
}cpuid_feature_info; |
static inline __u32 has_cpuid(void) |
static inline uint32_t has_cpuid(void) |
{ |
__u32 val, ret; |
uint32_t val, ret; |
__asm__ volatile ( |
"pushf\n" /* read flags */ |
97,7 → 97,7 |
return ret; |
} |
static inline void cpuid(__u32 cmd, struct cpu_info *info) |
static inline void cpuid(uint32_t cmd, struct cpu_info *info) |
{ |
__asm__ volatile ( |
"movl %4, %%eax\n" |
/kernel/trunk/arch/ia32/include/types.h |
---|
26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ia32 |
/** @addtogroup ia32 |
* @{ |
*/ |
/** @file |
37,28 → 37,28 |
#define NULL 0 |
typedef signed char __s8; |
typedef signed short __s16; |
typedef signed long __s32; |
typedef signed long long __s64; |
typedef signed char int8_t; |
typedef signed short int16_t; |
typedef signed long int32_t; |
typedef signed long long int64_t; |
typedef unsigned char __u8; |
typedef unsigned short __u16; |
typedef unsigned long __u32; |
typedef unsigned long long __u64; |
typedef unsigned char uint8_t; |
typedef unsigned short uint16_t; |
typedef unsigned long uint32_t; |
typedef unsigned long long uint64_t; |
typedef __u32 __address; |
typedef __u32 pfn_t; |
typedef uint32_t uintptr_t; |
typedef uint32_t pfn_t; |
typedef __u32 ipl_t; |
typedef uint32_t ipl_t; |
typedef __u32 __native; |
typedef __s32 __snative; |
typedef uint32_t unative_t; |
typedef int32_t native_t; |
typedef struct page_specifier pte_t; |
#endif |
/** @} |
/** @} |
*/ |
/kernel/trunk/arch/ia32/include/bios/bios.h |
---|
39,7 → 39,7 |
#define BIOS_EBDA_PTR 0x40e |
extern __address ebda; |
extern uintptr_t ebda; |
extern void bios_init(void); |
/kernel/trunk/arch/ia32/include/memstr.h |
---|
49,7 → 49,7 |
*/ |
static inline void * memcpy(void * dst, const void * src, size_t cnt) |
{ |
__native d0, d1, d2; |
unative_t d0, d1, d2; |
__asm__ __volatile__( |
/* copy all full dwords */ |
65,7 → 65,7 |
/* exit from asm block */ |
"1:\n" |
: "=&c" (d0), "=&D" (d1), "=&S" (d2) |
: "0" ((__native) (cnt / 4)), "g" ((__native) cnt), "1" ((__native) dst), "2" ((__native) src) |
: "0" ((unative_t) (cnt / 4)), "g" ((unative_t) cnt), "1" ((unative_t) dst), "2" ((unative_t) src) |
: "memory"); |
return dst; |
85,7 → 85,7 |
*/ |
static inline int memcmp(const void * src, const void * dst, size_t cnt) |
{ |
__u32 d0, d1, d2; |
uint32_t d0, d1, d2; |
int ret; |
__asm__ ( |
95,7 → 95,7 |
"addl $1, %0\n\t" |
"1:\n" |
: "=a" (ret), "=%S" (d0), "=&D" (d1), "=&c" (d2) |
: "0" (0), "1" ((__native) src), "2" ((__native) dst), "3" ((__native) cnt) |
: "0" (0), "1" ((unative_t) src), "2" ((unative_t) dst), "3" ((unative_t) cnt) |
); |
return ret; |
110,9 → 110,9 |
* @param cnt Number of words |
* @param x Value to fill |
*/ |
static inline void memsetw(__address dst, size_t cnt, __u16 x) |
static inline void memsetw(uintptr_t dst, size_t cnt, uint16_t x) |
{ |
__u32 d0, d1; |
uint32_t d0, d1; |
__asm__ __volatile__ ( |
"rep stosw\n\t" |
132,9 → 132,9 |
* @param cnt Number of bytes |
* @param x Value to fill |
*/ |
static inline void memsetb(__address dst, size_t cnt, __u8 x) |
static inline void memsetb(uintptr_t dst, size_t cnt, uint8_t x) |
{ |
__u32 d0, d1; |
uint32_t d0, d1; |
__asm__ __volatile__ ( |
"rep stosb\n\t" |
/kernel/trunk/arch/ia32/include/smp/apic.h |
---|
105,13 → 105,13 |
#define MODEL_CLUSTER 0x0 |
/** Interrupt Command Register. */ |
#define ICRlo (0x300/sizeof(__u32)) |
#define ICRhi (0x310/sizeof(__u32)) |
#define ICRlo (0x300/sizeof(uint32_t)) |
#define ICRhi (0x310/sizeof(uint32_t)) |
struct icr { |
union { |
__u32 lo; |
uint32_t lo; |
struct { |
__u8 vector; /**< Interrupt Vector. */ |
uint8_t vector; /**< Interrupt Vector. */ |
unsigned delmod : 3; /**< Delivery Mode. */ |
unsigned destmod : 1; /**< Destination Mode. */ |
unsigned delivs : 1; /**< Delivery status (RO). */ |
124,10 → 124,10 |
} __attribute__ ((packed)); |
}; |
union { |
__u32 hi; |
uint32_t hi; |
struct { |
unsigned : 24; /**< Reserved. */ |
__u8 dest; /**< Destination field. */ |
uint8_t dest; /**< Destination field. */ |
} __attribute__ ((packed)); |
}; |
} __attribute__ ((packed)); |
134,13 → 134,13 |
typedef struct icr icr_t; |
/* End Of Interrupt. */ |
#define EOI (0x0b0/sizeof(__u32)) |
#define EOI (0x0b0/sizeof(uint32_t)) |
/** Error Status Register. */ |
#define ESR (0x280/sizeof(__u32)) |
#define ESR (0x280/sizeof(uint32_t)) |
union esr { |
__u32 value; |
__u8 err_bitmap; |
uint32_t value; |
uint8_t err_bitmap; |
struct { |
unsigned send_checksum_error : 1; |
unsigned receive_checksum_error : 1; |
156,9 → 156,9 |
typedef union esr esr_t; |
/* Task Priority Register */ |
#define TPR (0x080/sizeof(__u32)) |
#define TPR (0x080/sizeof(uint32_t)) |
union tpr { |
__u32 value; |
uint32_t value; |
struct { |
unsigned pri_sc : 4; /**< Task Priority Sub-Class. */ |
unsigned pri : 4; /**< Task Priority. */ |
167,11 → 167,11 |
typedef union tpr tpr_t; |
/** Spurious-Interrupt Vector Register. */ |
#define SVR (0x0f0/sizeof(__u32)) |
#define SVR (0x0f0/sizeof(uint32_t)) |
union svr { |
__u32 value; |
uint32_t value; |
struct { |
__u8 vector; /**< Spurious Vector. */ |
uint8_t vector; /**< Spurious Vector. */ |
unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */ |
unsigned focus_checking : 1; /**< Focus Processor Checking. */ |
unsigned : 22; /**< Reserved. */ |
180,9 → 180,9 |
typedef union svr svr_t; |
/** Time Divide Configuration Register. */ |
#define TDCR (0x3e0/sizeof(__u32)) |
#define TDCR (0x3e0/sizeof(uint32_t)) |
union tdcr { |
__u32 value; |
uint32_t value; |
struct { |
unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
unsigned : 28; /**< Reserved. */ |
191,17 → 191,17 |
typedef union tdcr tdcr_t; |
/* Initial Count Register for Timer */ |
#define ICRT (0x380/sizeof(__u32)) |
#define ICRT (0x380/sizeof(uint32_t)) |
/* Current Count Register for Timer */ |
#define CCRT (0x390/sizeof(__u32)) |
#define CCRT (0x390/sizeof(uint32_t)) |
/** LVT Timer register. */ |
#define LVT_Tm (0x320/sizeof(__u32)) |
#define LVT_Tm (0x320/sizeof(uint32_t)) |
union lvt_tm { |
__u32 value; |
uint32_t value; |
struct { |
__u8 vector; /**< Local Timer Interrupt vector. */ |
uint8_t vector; /**< Local Timer Interrupt vector. */ |
unsigned : 4; /**< Reserved. */ |
unsigned delivs : 1; /**< Delivery status (RO). */ |
unsigned : 3; /**< Reserved. */ |
213,12 → 213,12 |
typedef union lvt_tm lvt_tm_t; |
/** LVT LINT registers. */ |
#define LVT_LINT0 (0x350/sizeof(__u32)) |
#define LVT_LINT1 (0x360/sizeof(__u32)) |
#define LVT_LINT0 (0x350/sizeof(uint32_t)) |
#define LVT_LINT1 (0x360/sizeof(uint32_t)) |
union lvt_lint { |
__u32 value; |
uint32_t value; |
struct { |
__u8 vector; /**< LINT Interrupt vector. */ |
uint8_t vector; /**< LINT Interrupt vector. */ |
unsigned delmod : 3; /**< Delivery Mode. */ |
unsigned : 1; /**< Reserved. */ |
unsigned delivs : 1; /**< Delivery status (RO). */ |
232,11 → 232,11 |
typedef union lvt_lint lvt_lint_t; |
/** LVT Error register. */ |
#define LVT_Err (0x370/sizeof(__u32)) |
#define LVT_Err (0x370/sizeof(uint32_t)) |
union lvt_error { |
__u32 value; |
uint32_t value; |
struct { |
__u8 vector; /**< Local Timer Interrupt vector. */ |
uint8_t vector; /**< Local Timer Interrupt vector. */ |
unsigned : 4; /**< Reserved. */ |
unsigned delivs : 1; /**< Delivery status (RO). */ |
unsigned : 3; /**< Reserved. */ |
247,18 → 247,18 |
typedef union lvt_error lvt_error_t; |
/** Local APIC ID Register. */ |
#define L_APIC_ID (0x020/sizeof(__u32)) |
#define L_APIC_ID (0x020/sizeof(uint32_t)) |
union l_apic_id { |
__u32 value; |
uint32_t value; |
struct { |
unsigned : 24; /**< Reserved. */ |
__u8 apic_id; /**< Local APIC ID. */ |
uint8_t apic_id; /**< Local APIC ID. */ |
} __attribute__ ((packed)); |
}; |
typedef union l_apic_id l_apic_id_t; |
/** Local APIC Version Register */ |
#define LAVR (0x030/sizeof(__u32)) |
#define LAVR (0x030/sizeof(uint32_t)) |
#define LAVR_Mask 0xff |
#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
#define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
265,20 → 265,20 |
#define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
/** Logical Destination Register. */ |
#define LDR (0x0d0/sizeof(__u32)) |
#define LDR (0x0d0/sizeof(uint32_t)) |
union ldr { |
__u32 value; |
uint32_t value; |
struct { |
unsigned : 24; /**< Reserved. */ |
__u8 id; /**< Logical APIC ID. */ |
uint8_t id; /**< Logical APIC ID. */ |
} __attribute__ ((packed)); |
}; |
typedef union ldr ldr_t; |
/** Destination Format Register. */ |
#define DFR (0x0e0/sizeof(__u32)) |
#define DFR (0x0e0/sizeof(uint32_t)) |
union dfr { |
__u32 value; |
uint32_t value; |
struct { |
unsigned : 28; /**< Reserved, all ones. */ |
unsigned model : 4; /**< Model. */ |
287,8 → 287,8 |
typedef union dfr dfr_t; |
/* IO APIC */ |
#define IOREGSEL (0x00/sizeof(__u32)) |
#define IOWIN (0x10/sizeof(__u32)) |
#define IOREGSEL (0x00/sizeof(uint32_t)) |
#define IOWIN (0x10/sizeof(uint32_t)) |
#define IOAPICID 0x00 |
#define IOAPICVER 0x01 |
297,9 → 297,9 |
/** I/O Register Select Register. */ |
union io_regsel { |
__u32 value; |
uint32_t value; |
struct { |
__u8 reg_addr; /**< APIC Register Address. */ |
uint8_t reg_addr; /**< APIC Register Address. */ |
unsigned : 24; /**< Reserved. */ |
} __attribute__ ((packed)); |
}; |
308,9 → 308,9 |
/** I/O Redirection Register. */ |
struct io_redirection_reg { |
union { |
__u32 lo; |
uint32_t lo; |
struct { |
__u8 intvec; /**< Interrupt Vector. */ |
uint8_t intvec; /**< Interrupt Vector. */ |
unsigned delmod : 3; /**< Delivery Mode. */ |
unsigned destmod : 1; /**< Destination mode. */ |
unsigned delivs : 1; /**< Delivery status (RO). */ |
322,10 → 322,10 |
} __attribute__ ((packed)); |
}; |
union { |
__u32 hi; |
uint32_t hi; |
struct { |
unsigned : 24; /**< Reserved. */ |
__u8 dest : 8; /**< Destination Field. */ |
uint8_t dest : 8; /**< Destination Field. */ |
} __attribute__ ((packed)); |
}; |
335,7 → 335,7 |
/** IO APIC Identification Register. */ |
union io_apic_id { |
__u32 value; |
uint32_t value; |
struct { |
unsigned : 24; /**< Reserved. */ |
unsigned apic_id : 4; /**< IO APIC ID. */ |
344,25 → 344,25 |
}; |
typedef union io_apic_id io_apic_id_t; |
extern volatile __u32 *l_apic; |
extern volatile __u32 *io_apic; |
extern volatile uint32_t *l_apic; |
extern volatile uint32_t *io_apic; |
extern __u32 apic_id_mask; |
extern uint32_t apic_id_mask; |
extern void apic_init(void); |
extern void l_apic_init(void); |
extern void l_apic_eoi(void); |
extern int l_apic_broadcast_custom_ipi(__u8 vector); |
extern int l_apic_send_init_ipi(__u8 apicid); |
extern int l_apic_broadcast_custom_ipi(uint8_t vector); |
extern int l_apic_send_init_ipi(uint8_t apicid); |
extern void l_apic_debug(void); |
extern __u8 l_apic_id(void); |
extern uint8_t l_apic_id(void); |
extern __u32 io_apic_read(__u8 address); |
extern void io_apic_write(__u8 address , __u32 x); |
extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags); |
extern void io_apic_disable_irqs(__u16 irqmask); |
extern void io_apic_enable_irqs(__u16 irqmask); |
extern uint32_t io_apic_read(uint8_t address); |
extern void io_apic_write(uint8_t address , uint32_t x); |
extern void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags); |
extern void io_apic_disable_irqs(uint16_t irqmask); |
extern void io_apic_enable_irqs(uint16_t irqmask); |
#endif |
/kernel/trunk/arch/ia32/include/smp/mps.h |
---|
45,79 → 45,79 |
#define CT_EXT_ENTRY_LEN 1 |
struct mps_fs { |
__u32 signature; |
__u32 configuration_table; |
__u8 length; |
__u8 revision; |
__u8 checksum; |
__u8 config_type; |
__u8 mpfib2; |
__u8 mpfib3; |
__u8 mpfib4; |
__u8 mpfib5; |
uint32_t signature; |
uint32_t configuration_table; |
uint8_t length; |
uint8_t revision; |
uint8_t checksum; |
uint8_t config_type; |
uint8_t mpfib2; |
uint8_t mpfib3; |
uint8_t mpfib4; |
uint8_t mpfib5; |
} __attribute__ ((packed)); |
struct mps_ct { |
__u32 signature; |
__u16 base_table_length; |
__u8 revision; |
__u8 checksum; |
__u8 oem_id[8]; |
__u8 product_id[12]; |
__u32 oem_table; |
__u16 oem_table_size; |
__u16 entry_count; |
__u32 l_apic; |
__u16 ext_table_length; |
__u8 ext_table_checksum; |
__u8 xxx; |
__u8 base_table[0]; |
uint32_t signature; |
uint16_t base_table_length; |
uint8_t revision; |
uint8_t checksum; |
uint8_t oem_id[8]; |
uint8_t product_id[12]; |
uint32_t oem_table; |
uint16_t oem_table_size; |
uint16_t entry_count; |
uint32_t l_apic; |
uint16_t ext_table_length; |
uint8_t ext_table_checksum; |
uint8_t xxx; |
uint8_t base_table[0]; |
} __attribute__ ((packed)); |
struct __processor_entry { |
__u8 type; |
__u8 l_apic_id; |
__u8 l_apic_version; |
__u8 cpu_flags; |
__u8 cpu_signature[4]; |
__u32 feature_flags; |
__u32 xxx[2]; |
uint8_t type; |
uint8_t l_apic_id; |
uint8_t l_apic_version; |
uint8_t cpu_flags; |
uint8_t cpu_signature[4]; |
uint32_t feature_flags; |
uint32_t xxx[2]; |
} __attribute__ ((packed)); |
struct __bus_entry { |
__u8 type; |
__u8 bus_id; |
__u8 bus_type[6]; |
uint8_t type; |
uint8_t bus_id; |
uint8_t bus_type[6]; |
} __attribute__ ((packed)); |
struct __io_apic_entry { |
__u8 type; |
__u8 io_apic_id; |
__u8 io_apic_version; |
__u8 io_apic_flags; |
__u32 io_apic; |
uint8_t type; |
uint8_t io_apic_id; |
uint8_t io_apic_version; |
uint8_t io_apic_flags; |
uint32_t io_apic; |
} __attribute__ ((packed)); |
struct __io_intr_entry { |
__u8 type; |
__u8 intr_type; |
__u8 poel; |
__u8 xxx; |
__u8 src_bus_id; |
__u8 src_bus_irq; |
__u8 dst_io_apic_id; |
__u8 dst_io_apic_pin; |
uint8_t type; |
uint8_t intr_type; |
uint8_t poel; |
uint8_t xxx; |
uint8_t src_bus_id; |
uint8_t src_bus_irq; |
uint8_t dst_io_apic_id; |
uint8_t dst_io_apic_pin; |
} __attribute__ ((packed)); |
struct __l_intr_entry { |
__u8 type; |
__u8 intr_type; |
__u8 poel; |
__u8 xxx; |
__u8 src_bus_id; |
__u8 src_bus_irq; |
__u8 dst_l_apic_id; |
__u8 dst_l_apic_pin; |
uint8_t type; |
uint8_t intr_type; |
uint8_t poel; |
uint8_t xxx; |
uint8_t src_bus_id; |
uint8_t src_bus_irq; |
uint8_t dst_l_apic_id; |
uint8_t dst_l_apic_pin; |
} __attribute__ ((packed)); |
/kernel/trunk/arch/ia32/include/smp/smp.h |
---|
43,7 → 43,7 |
count_t (* cpu_count)(void); /**< Return number of detected processors. */ |
bool (* cpu_enabled)(index_t i); /**< Check whether the processor of index i is enabled. */ |
bool (*cpu_bootstrap)(index_t i); /**< Check whether the processor of index i is BSP. */ |
__u8 (*cpu_apic_id)(index_t i); /**< Return APIC ID of the processor of index i. */ |
uint8_t (*cpu_apic_id)(index_t i); /**< Return APIC ID of the processor of index i. */ |
int (*irq_to_pin)(int irq); /**< Return mapping between irq and APIC pin. */ |
}; |
/kernel/trunk/arch/ia32/include/atomic.h |
---|
83,8 → 83,8 |
#define atomic_preinc(val) (atomic_postinc(val)+1) |
#define atomic_predec(val) (atomic_postdec(val)-1) |
static inline __u32 test_and_set(atomic_t *val) { |
__u32 v; |
static inline uint32_t test_and_set(atomic_t *val) { |
uint32_t v; |
__asm__ volatile ( |
"movl $1, %0\n" |
98,7 → 98,7 |
/** ia32 specific fast spinlock */ |
static inline void atomic_lock_arch(atomic_t *val) |
{ |
__u32 tmp; |
uint32_t tmp; |
preemption_disable(); |
__asm__ volatile ( |
/kernel/trunk/arch/ia32/include/pm.h |
---|
85,8 → 85,8 |
#include <arch/context.h> |
struct ptr_16_32 { |
__u16 limit; |
__u32 base; |
uint16_t limit; |
uint32_t base; |
} __attribute__ ((packed)); |
typedef struct ptr_16_32 ptr_16_32_t; |
114,45 → 114,45 |
typedef struct idescriptor idescriptor_t; |
struct tss { |
__u16 link; |
uint16_t link; |
unsigned : 16; |
__u32 esp0; |
__u16 ss0; |
uint32_t esp0; |
uint16_t ss0; |
unsigned : 16; |
__u32 esp1; |
__u16 ss1; |
uint32_t esp1; |
uint16_t ss1; |
unsigned : 16; |
__u32 esp2; |
__u16 ss2; |
uint32_t esp2; |
uint16_t ss2; |
unsigned : 16; |
__u32 cr3; |
__u32 eip; |
__u32 eflags; |
__u32 eax; |
__u32 ecx; |
__u32 edx; |
__u32 ebx; |
__u32 esp; |
__u32 ebp; |
__u32 esi; |
__u32 edi; |
__u16 es; |
uint32_t cr3; |
uint32_t eip; |
uint32_t eflags; |
uint32_t eax; |
uint32_t ecx; |
uint32_t edx; |
uint32_t ebx; |
uint32_t esp; |
uint32_t ebp; |
uint32_t esi; |
uint32_t edi; |
uint16_t es; |
unsigned : 16; |
__u16 cs; |
uint16_t cs; |
unsigned : 16; |
__u16 ss; |
uint16_t ss; |
unsigned : 16; |
__u16 ds; |
uint16_t ds; |
unsigned : 16; |
__u16 fs; |
uint16_t fs; |
unsigned : 16; |
__u16 gs; |
uint16_t gs; |
unsigned : 16; |
__u16 ldtr; |
uint16_t ldtr; |
unsigned : 16; |
unsigned : 16; |
__u16 iomap_base; |
__u8 iomap[TSS_IOMAP_SIZE]; |
uint16_t iomap_base; |
uint8_t iomap[TSS_IOMAP_SIZE]; |
} __attribute__ ((packed)); |
typedef struct tss tss_t; |
165,14 → 165,14 |
extern void pm_init(void); |
extern void gdt_setbase(descriptor_t *d, __address base); |
extern void gdt_setlimit(descriptor_t *d, __u32 limit); |
extern void gdt_setbase(descriptor_t *d, uintptr_t base); |
extern void gdt_setlimit(descriptor_t *d, uint32_t limit); |
extern void idt_init(void); |
extern void idt_setoffset(idescriptor_t *d, __address offset); |
extern void idt_setoffset(idescriptor_t *d, uintptr_t offset); |
extern void tss_initialize(tss_t *t); |
extern void set_tls_desc(__address tls); |
extern void set_tls_desc(uintptr_t tls); |
#endif /* __ASM__ */ |
/kernel/trunk/arch/ia32/include/boot/memmap.h |
---|
58,16 → 58,16 |
#include <arch/types.h> |
struct e820memmap_ { |
__u64 base_address; |
__u64 size; |
__u32 type; |
uint64_t base_address; |
uint64_t size; |
uint32_t type; |
} __attribute__ ((packed)); |
extern struct e820memmap_ e820table[MEMMAP_E820_MAX_RECORDS]; |
extern __u8 e820counter; |
extern uint8_t e820counter; |
extern __u32 e801memorysize; /**< Size of available memory in KB. */ |
extern uint32_t e801memorysize; /**< Size of available memory in KB. */ |
#endif |
/kernel/trunk/arch/ia32/include/proc/thread.h |
---|
38,7 → 38,7 |
#include <arch/types.h> |
typedef struct { |
__native tls; |
unative_t tls; |
} thread_arch_t; |
#endif |
/kernel/trunk/arch/ia32/include/asm.h |
---|
40,7 → 40,7 |
#include <arch/types.h> |
#include <config.h> |
extern __u32 interrupt_handler_size; |
extern uint32_t interrupt_handler_size; |
extern void paging_on(void); |
49,8 → 49,8 |
extern void enable_l_apic_in_msr(void); |
extern void asm_delay_loop(__u32 t); |
extern void asm_fake_loop(__u32 t); |
extern void asm_delay_loop(uint32_t t); |
extern void asm_fake_loop(uint32_t t); |
/** Halt CPU |
60,14 → 60,14 |
static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \ |
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
{ \ |
__native res; \ |
unative_t res; \ |
__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
return res; \ |
} |
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \ |
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
{ \ |
__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
} |
98,7 → 98,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
/** Word to port |
* |
107,7 → 107,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
/** Double word to port |
* |
116,7 → 116,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
/** Byte from port |
* |
125,7 → 125,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
/** Word from port |
* |
134,7 → 134,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
/** Double word from port |
* |
143,7 → 143,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
/** Enable interrupts. |
* |
219,9 → 219,9 |
* The stack is assumed to be STACK_SIZE bytes long. |
* The stack must start on page boundary. |
*/ |
static inline __address get_stack_base(void) |
static inline uintptr_t get_stack_base(void) |
{ |
__address v; |
uintptr_t v; |
__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
228,9 → 228,9 |
return v; |
} |
static inline __u64 rdtsc(void) |
static inline uint64_t rdtsc(void) |
{ |
__u64 v; |
uint64_t v; |
__asm__ volatile("rdtsc\n" : "=A" (v)); |
238,9 → 238,9 |
} |
/** Return current IP address */ |
static inline __address * get_ip() |
static inline uintptr_t * get_ip() |
{ |
__address *ip; |
uintptr_t *ip; |
__asm__ volatile ( |
"mov %%eip, %0" |
253,9 → 253,9 |
* |
* @param addr Address on a page whose TLB entry is to be invalidated. |
*/ |
static inline void invlpg(__address addr) |
static inline void invlpg(uintptr_t addr) |
{ |
__asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr)); |
__asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
} |
/** Load GDTR register from memory. |
289,7 → 289,7 |
* |
* @param sel Selector specifying descriptor of TSS segment. |
*/ |
static inline void tr_load(__u16 sel) |
static inline void tr_load(uint16_t sel) |
{ |
__asm__ volatile ("ltr %0" : : "r" (sel)); |
} |
/kernel/trunk/arch/ia32/include/faddr.h |
---|
37,7 → 37,7 |
#include <arch/types.h> |
#define FADDR(fptr) ((__address) (fptr)) |
#define FADDR(fptr) ((uintptr_t) (fptr)) |
#endif |
/kernel/trunk/arch/ia32/include/mm/frame.h |
---|
44,7 → 44,7 |
#include <arch/types.h> |
extern __address last_frame; |
extern uintptr_t last_frame; |
extern void frame_arch_init(void); |
/kernel/trunk/arch/ia32/include/mm/page.h |
---|
43,8 → 43,8 |
#ifdef KERNEL |
#ifndef __ASM__ |
# define KA2PA(x) (((__address) (x)) - 0x80000000) |
# define PA2KA(x) (((__address) (x)) + 0x80000000) |
# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
#else |
# define KA2PA(x) ((x) - 0x80000000) |
# define PA2KA(x) ((x) + 0x80000000) |
67,9 → 67,9 |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)((((pte_t *)(ptl0))[(i)].frame_address)<<12)) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((__address)((((pte_t *)(ptl3))[(i)].frame_address)<<12)) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)((((pte_t *)(ptl3))[(i)].frame_address)<<12)) |
#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((__address) (ptl0))) |
#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((uintptr_t) (ptl0))) |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].frame_address = (a)>>12) |
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
85,7 → 85,7 |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) |
#define PTE_VALID_ARCH(p) (*((__u32 *) (p)) != 0) |
#define PTE_VALID_ARCH(p) (*((uint32_t *) (p)) != 0) |
#define PTE_PRESENT_ARCH(p) ((p)->present != 0) |
#define PTE_GET_FRAME_ARCH(p) ((p)->frame_address<<FRAME_WIDTH) |
#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0) |
/kernel/trunk/arch/ia32/include/context.h |
---|
52,12 → 52,12 |
* function calls. |
*/ |
struct context { |
__address sp; |
__address pc; |
__u32 ebx; |
__u32 esi; |
__u32 edi; |
__u32 ebp; |
uintptr_t sp; |
uintptr_t pc; |
uint32_t ebx; |
uint32_t esi; |
uint32_t edi; |
uint32_t ebp; |
ipl_t ipl; |
} __attribute__ ((packed)); |
/kernel/trunk/arch/ia32/include/drivers/i8259.h |
---|
47,8 → 47,8 |
#define PIC_ICW1 (1<<4) |
extern void i8259_init(void); |
extern void pic_enable_irqs(__u16 irqmask); |
extern void pic_disable_irqs(__u16 irqmask); |
extern void pic_enable_irqs(uint16_t irqmask); |
extern void pic_disable_irqs(uint16_t irqmask); |
extern void pic_eoi(void); |
#endif |
/kernel/trunk/arch/ia32/include/drivers/i8042.h |
---|
45,22 → 45,22 |
#define i8042_DATA 0x60 |
#define i8042_STATUS 0x64 |
static inline void i8042_data_write(__u8 data) |
static inline void i8042_data_write(uint8_t data) |
{ |
outb(i8042_DATA, data); |
} |
static inline __u8 i8042_data_read(void) |
static inline uint8_t i8042_data_read(void) |
{ |
return inb(i8042_DATA); |
} |
static inline __u8 i8042_status_read(void) |
static inline uint8_t i8042_status_read(void) |
{ |
return inb(i8042_STATUS); |
} |
static inline void i8042_command_write(__u8 command) |
static inline void i8042_command_write(uint8_t command) |
{ |
outb(i8042_STATUS, command); |
} |