40,7 → 40,7 |
#include <arch/types.h> |
#include <config.h> |
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extern __u32 interrupt_handler_size; |
extern uint32_t interrupt_handler_size; |
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extern void paging_on(void); |
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49,8 → 49,8 |
extern void enable_l_apic_in_msr(void); |
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extern void asm_delay_loop(__u32 t); |
extern void asm_fake_loop(__u32 t); |
extern void asm_delay_loop(uint32_t t); |
extern void asm_fake_loop(uint32_t t); |
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/** Halt CPU |
60,14 → 60,14 |
static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
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#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \ |
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
{ \ |
__native res; \ |
unative_t res; \ |
__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
return res; \ |
} |
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \ |
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
{ \ |
__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
} |
98,7 → 98,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
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/** Word to port |
* |
107,7 → 107,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
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/** Double word to port |
* |
116,7 → 116,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
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/** Byte from port |
* |
125,7 → 125,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
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/** Word from port |
* |
134,7 → 134,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
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/** Double word from port |
* |
143,7 → 143,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
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/** Enable interrupts. |
* |
219,9 → 219,9 |
* The stack is assumed to be STACK_SIZE bytes long. |
* The stack must start on page boundary. |
*/ |
static inline __address get_stack_base(void) |
static inline uintptr_t get_stack_base(void) |
{ |
__address v; |
uintptr_t v; |
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__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
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228,9 → 228,9 |
return v; |
} |
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static inline __u64 rdtsc(void) |
static inline uint64_t rdtsc(void) |
{ |
__u64 v; |
uint64_t v; |
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__asm__ volatile("rdtsc\n" : "=A" (v)); |
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238,9 → 238,9 |
} |
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/** Return current IP address */ |
static inline __address * get_ip() |
static inline uintptr_t * get_ip() |
{ |
__address *ip; |
uintptr_t *ip; |
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__asm__ volatile ( |
"mov %%eip, %0" |
253,9 → 253,9 |
* |
* @param addr Address on a page whose TLB entry is to be invalidated. |
*/ |
static inline void invlpg(__address addr) |
static inline void invlpg(uintptr_t addr) |
{ |
__asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr)); |
__asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
} |
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/** Load GDTR register from memory. |
289,7 → 289,7 |
* |
* @param sel Selector specifying descriptor of TSS segment. |
*/ |
static inline void tr_load(__u16 sel) |
static inline void tr_load(uint16_t sel) |
{ |
__asm__ volatile ("ltr %0" : : "r" (sel)); |
} |