/kernel/trunk/arch/amd64/src/fpu_context.c |
---|
34,10 → 34,6 |
/** Save FPU (mmx, sse) context using fxsave instruction */ |
void fpu_context_save(fpu_context_t *fctx) |
{ |
/* Align on 16-byte boundary */ |
if (((__u64)fctx) & 0xf) |
fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1); |
__asm__ volatile ( |
"fxsave %0" |
: "=m"(*fctx) |
47,9 → 43,6 |
/** Restore FPU (mmx,sse) context using fxrstor instruction */ |
void fpu_context_restore(fpu_context_t *fctx) |
{ |
/* Align on 16-byte boundary */ |
if (((__u64)fctx) & 0xf) |
fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1); |
__asm__ volatile ( |
"fxrstor %0" |
: "=m"(*fctx) |
56,7 → 49,7 |
); |
} |
void fpu_init(fpu_context_t *fctx) |
void fpu_init() |
{ |
/* TODO: Zero all SSE, MMX etc. registers */ |
__asm__ volatile ( |
/kernel/trunk/arch/mips32/include/fpu_context.h |
---|
31,6 → 31,9 |
#include <arch/types.h> |
#define ARCH_HAS_FPU |
#define FPU_CONTEXT_ALIGN sizeof(__native) |
struct fpu_context { |
__native dregs[32]; |
__native cregs[32]; |
/kernel/trunk/arch/mips32/src/fpu_context.c |
---|
50,7 → 50,7 |
#endif |
} |
void fpu_init(fpu_context_t *fctx) |
void fpu_init() |
{ |
/* TODO: Zero all registers */ |
} |
/kernel/trunk/arch/ia32/include/fpu_context.h |
---|
31,9 → 31,12 |
#include <arch/types.h> |
#define ARCH_HAS_FPU |
#define FPU_CONTEXT_ALIGN 16 |
struct fpu_context { |
/* TODO: We need malloc that aligns structures on 16-byte boundary */ |
__u8 fpu[512+16]; /* FXSAVE & FXRSTOR storage area */ |
__u8 fpu[512]; /* FXSAVE & FXRSTOR storage area */ |
}; |
/kernel/trunk/arch/ia32/src/fpu_context.c |
---|
48,7 → 48,7 |
); |
} |
void fpu_init(fpu_context_t *fctx) |
void fpu_init() |
{ |
__asm__ volatile ( |
"fninit;" |