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Ignore whitespace Rev 1250 → Rev 1251

/kernel/trunk/arch/amd64/include/asm.h
207,7 → 207,7
*/
static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
{
__asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
__asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
}
 
/** Store GDTR register to memory.
216,7 → 216,7
*/
static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
{
__asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
__asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
}
 
/** Load IDTR register from memory.
225,7 → 225,7
*/
static inline void idtr_load(struct ptr_16_64 *idtr_reg)
{
__asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
__asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
}
 
/** Load TR from descriptor table.
/kernel/trunk/arch/amd64/src/pm.c
213,7 → 213,7
tss_desc->dpl = PL_KERNEL;
gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
gdt_tss_setlimit(&gdt_p[TSS_DES], sizeof(tss_t) - 1);
gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
 
gdtr_load(&gdtr);
idtr_load(&idtr);
/kernel/trunk/arch/ia32/include/smp/apic.h
127,7 → 127,7
} __attribute__ ((packed));
typedef struct icr icr_t;
 
/* End Of Interrupt */
/* End Of Interrupt. */
#define EOI (0x0b0/sizeof(__u32))
 
/** Error Status Register. */
251,7 → 251,7
};
typedef union l_apic_id l_apic_id_t;
 
/* Local APIC Version Register */
/** Local APIC Version Register */
#define LAVR (0x030/sizeof(__u32))
#define LAVR_Mask 0xff
#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1)
263,7 → 263,7
union ldr {
__u32 value;
struct {
unsigned : 24; /**< Reserver. */
unsigned : 24; /**< Reserved. */
__u8 id; /**< Logical APIC ID. */
} __attribute__ ((packed));
};
319,7 → 319,7
__u32 hi;
struct {
unsigned : 24; /**< Reserved. */
__u8 dest : 8; /**< Destination Field. */
__u8 dest : 8; /**< Destination Field. */
} __attribute__ ((packed));
};
/kernel/trunk/arch/ia32/include/asm.h
258,7 → 258,7
*/
static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
{
__asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
__asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
}
 
/** Store GDTR register to memory.
267,7 → 267,7
*/
static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
{
__asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
__asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
}
 
/** Load IDTR register from memory.
276,7 → 276,7
*/
static inline void idtr_load(ptr_16_32_t *idtr_reg)
{
__asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
__asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg));
}
 
/** Load TR from descriptor table.
/kernel/trunk/arch/ia32/src/pm.c
199,10 → 199,10
gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
gdt_p[TSS_DES].special = 1;
gdt_p[TSS_DES].granularity = 1;
gdt_p[TSS_DES].granularity = 0;
gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
gdt_setlimit(&gdt_p[TSS_DES], sizeof(tss_t) - 1);
gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
 
/*
* As of this moment, the current CPU has its own GDT pointing
210,7 → 210,7
*/
tr_load(selector(TSS_DES));
clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */
clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */
clean_AM_flag(); /* Disable alignment check */
}
 
/kernel/trunk/arch/ia32/src/proc/scheduler.c
36,6 → 36,7
#include <arch/pm.h>
#include <arch/asm.h>
#include <adt/bitmap.h>
#include <print.h>
 
/** Perform ia32 specific tasks needed before the new task is run.
*
55,7 → 56,7
spinlock_lock(&TASK->lock);
if ((bits = TASK->arch.iomap.bits)) {
bitmap_t iomap;
 
ASSERT(TASK->arch.iomap.map);
bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8);
bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);