/kernel/trunk/arch/ia64/include/mm/tlb.h |
---|
41,7 → 41,8 |
/** Data and instruction Translation Register indices. */ |
#define DTR_KERNEL 0 |
#define ITR_KERNEL 0 |
#define DTR_KSTACK 1 |
#define DTR_KSTACK1 1 |
#define DTR_KSTACK2 2 |
/** Portion of TLB insertion format data structure. */ |
union tlb_entry { |
/kernel/trunk/arch/ia64/include/context.h |
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36,7 → 36,7 |
#include <arch/stack.h> |
/* |
* context_save() and context_restore() are both leaf procedures. |
* context_save_arch() and context_restore_arch() are both leaf procedures. |
* No need to allocate scratch area. |
* |
* One item is put onto the stack to support get_stack_base(). |
47,12 → 47,14 |
#undef context_set |
#endif |
/*RSE stack should begin under bottom of stack @ kernel*/ |
#define context_set(c, _pc, stack, size) \ |
(c)->pc = (__address) _pc; \ |
(c)->bsp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) ; \ |
(c)->ar_pfs &= PFM_MASK; \ |
(c)->sp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - SP_DELTA; |
/* RSE stack starts at the bottom of memory stack. */ |
#define context_set(c, _pc, stack, size) \ |
do { \ |
(c)->pc = (__address) _pc; \ |
(c)->bsp = ((__address) stack) + ALIGN_UP((size), REGISTER_STACK_ALIGNMENT); \ |
(c)->ar_pfs &= PFM_MASK; \ |
(c)->sp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - SP_DELTA; \ |
} while (0); |
/* |
* Only save registers that must be preserved across |
122,6 → 124,4 |
ipl_t ipl; |
}; |
#endif |
/kernel/trunk/arch/ia64/src/ivt.S |
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32,11 → 32,8 |
#include <arch/mm/page.h> |
#include <align.h> |
#define FRS_TO_SAVE 30 |
#define STACK_ITEMS (19 + FRS_TO_SAVE*2) |
//#define STACK_ITEMS 19 |
/* 30*2 for FPU registers */ |
#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT) |
#if (STACK_ITEMS % 2 == 0) |
/kernel/trunk/arch/ia64/src/proc/scheduler.c |
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43,12 → 43,13 |
base = ALIGN_DOWN(config.base, 1<<KERNEL_PAGE_WIDTH); |
if ((__address) THREAD->kstack < base || (__address) THREAD->kstack > base + (1<<KERNEL_PAGE_WIDTH)) { |
if ((__address) THREAD->kstack < base || (__address) THREAD->kstack > base + (1<<(KERNEL_PAGE_WIDTH))) { |
/* |
* Kernel stack of this thread is not mapped by DTR[TR_KERNEL]. |
* Use DTR[TR_KSTACK] to map it. |
* Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it. |
*/ |
dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK); |
dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1); |
dtlb_kernel_mapping_insert((__address) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2); |
} |
/* |