/kernel/trunk/arch/mips32/include/fpu_context.h |
---|
31,6 → 31,7 |
#include <arch/types.h> |
#define ARCH_HAS_FPU |
#define FPU_CONTEXT_ALIGN sizeof(__native) |
struct fpu_context { |
/kernel/trunk/arch/mips32/src/fpu_context.c |
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34,7 → 34,7 |
void fpu_disable(void) |
{ |
#ifdef ARCH_HAS_FPU |
#ifdef HAVE_FPU |
cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit); |
if (THREAD && THREAD->pstate) |
THREAD->pstate->status &= ~cp0_status_fpu_bit; |
43,7 → 43,7 |
void fpu_enable(void) |
{ |
#ifdef ARCH_HAS_FPU |
#ifdef HAVE_FPU |
cp0_status_write(cp0_status_read() | cp0_status_fpu_bit); |
if (THREAD && THREAD->pstate) |
THREAD->pstate->status |= cp0_status_fpu_bit; |
/kernel/trunk/arch/mips32/src/asm.S |
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156,7 → 156,7 |
.global fpu_context_save |
fpu_context_save: |
#ifdef ARCH_HAS_FPU |
#ifdef HAVE_FPU |
fpu_gp_save 0,$a0 |
fpu_gp_save 1,$a0 |
fpu_gp_save 2,$a0 |
227,7 → 227,7 |
.global fpu_context_restore |
fpu_context_restore: |
#ifdef ARCH_HAS_FPU |
#ifdef HAVE_FPU |
fpu_gp_restore 0,$a0 |
fpu_gp_restore 1,$a0 |
fpu_gp_restore 2,$a0 |
/kernel/trunk/arch/mips32/Makefile.inc |
---|
72,7 → 72,7 |
TARGET = mips-sgi-irix5 |
TOOLCHAIN_DIR = /usr/local/mips/bin |
KERNEL_LOAD_ADDRESS = 0x88002000 |
CFLAGS += -EB -DBIG_ENDIAN -DARCH_HAS_FPU -march=r4600 |
CFLAGS += -EB -DBIG_ENDIAN -DHAVE_FPU -march=r4600 |
INIT_ADDRESS = 0 |
INIT_SIZE = 0 |
endif |
79,7 → 79,7 |
ifeq ($(MIPS_MACHINE),lgxemul) |
BFD_NAME=elf32-tradlittlemips |
BFD = ecoff-littlemips |
CFLAGS += -DARCH_HAS_FPU -mips3 |
CFLAGS += -DHAVE_FPU -mips3 |
INIT_ADDRESS = 0x1800000 |
endif |
ifeq ($(MIPS_MACHINE),bgxemul) |
87,7 → 87,7 |
BFD = ecoff-bigmips |
TARGET = mips-sgi-irix5 |
TOOLCHAIN_DIR = /usr/local/mips/bin |
CFLAGS += -EB -DBIG_ENDIAN -DARCH_HAS_FPU -mips3 |
CFLAGS += -EB -DBIG_ENDIAN -DHAVE_FPU -mips3 |
INIT_ADDRESS = 0x1800000 |
endif |
ifeq ($(MIPS_MACHINE),simics) |