/kernel/trunk/arch/sparc64/include/asm.h |
---|
131,10 → 131,9 |
*/ |
static inline void asi_u64_write(asi_t asi, __address va, __u64 v) |
{ |
__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi)); |
__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory"); |
} |
void cpu_halt(void); |
void cpu_sleep(void); |
void asm_delay_loop(__u32 t); |
/kernel/trunk/arch/sparc64/include/mm/tlb.h |
---|
31,6 → 31,7 |
#include <arch/mm/tte.h> |
#include <arch/asm.h> |
#include <arch/barrier.h> |
#include <arch/types.h> |
#include <typedefs.h> |
97,6 → 98,7 |
} __attribute__ ((packed)); |
}; |
typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
/** Read IMMU TLB Data Access Register. |
* |
134,7 → 136,7 |
* |
* @return Current value of specified IMMU TLB Tag Read Register. |
*/ |
static inline __u64 itlb_tag_read(index_t entry) |
static inline __u64 itlb_tag_read_read(index_t entry) |
{ |
tlb_tag_read_addr_t tag; |
149,7 → 151,7 |
* |
* @return Current value of specified DMMU TLB Tag Read Register. |
*/ |
static inline __u64 dtlb_tag_read(index_t entry) |
static inline __u64 dtlb_tag_read_read(index_t entry) |
{ |
tlb_tag_read_addr_t tag; |
158,4 → 160,44 |
return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
} |
/** Write IMMU TLB Tag Access Register. |
* |
* @param v Value to be written. |
*/ |
static inline void itlb_tag_access_write(__u64 v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
flush(); |
} |
/** Write DMMU TLB Tag Access Register. |
* |
* @param v Value to be written. |
*/ |
static inline void dtlb_tag_access_write(__u64 v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
flush(); |
} |
/** Write IMMU TLB Data in Register. |
* |
* @param v Value to be written. |
*/ |
static inline void itlb_data_in_write(__u64 v) |
{ |
asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
flush(); |
} |
/** Write DMMU TLB Data in Register. |
* |
* @param v Value to be written. |
*/ |
static inline void dtlb_data_in_write(__u64 v) |
{ |
asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
flush(); |
} |
#endif |
/kernel/trunk/arch/sparc64/include/barrier.h |
---|
39,6 → 39,16 |
#define read_barrier() |
#define write_barrier() |
#define flush() __asm__ volatile ("flush\n" ::: "memory") |
/** Flush Instruction Memory. */ |
static inline void flush(void) |
{ |
/* |
* The FLUSH instruction takes address parameter, |
* but JPS1 implementations are free to ignore it. |
* The only requirement is that it is a valid address |
* as it is passed to D-MMU. |
*/ |
__asm__ volatile ("flush %sp\n"); /* %sp is guaranteed to reference mapped memory */ |
} |
#endif |
/kernel/trunk/arch/sparc64/src/mm/tlb.c |
---|
44,9 → 44,9 |
printf("I-TLB contents:\n"); |
for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
d.value = itlb_data_access_read(i); |
t.value = itlb_tag_read(i); |
t.value = itlb_tag_read_read(i); |
printf("%d: va=%X, context=%d, v=%d, size=%X, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
printf("%d: va=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
i, t.va, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pa, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
} |
53,9 → 53,9 |
printf("D-TLB contents:\n"); |
for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
d.value = dtlb_data_access_read(i); |
t.value = dtlb_tag_read(i); |
t.value = dtlb_tag_read_read(i); |
printf("%d: va=%X, context=%d, v=%d, size=%X, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
printf("%d: va=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
i, t.va, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pa, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
} |