47,6 → 47,7 |
count_t bits; |
ptr_16_64_t cpugdtr; |
descriptor_t *gdt_p; |
tss_descriptor_t *tss_desc; |
|
/* |
* Switch the I/O Permission Bitmap, if necessary. |
61,10 → 62,10 |
bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8); |
bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits); |
/* |
* It is safe to set the trailing four bits because of the extra |
* It is safe to set the trailing eight bits because of the extra |
* convenience byte in TSS_IOMAP_SIZE. |
*/ |
bitmap_set_range(&iomap, TASK->arch.iomap.bits, 4); |
bitmap_set_range(&iomap, TASK->arch.iomap.bits, 8); |
} |
spinlock_unlock(&TASK->lock); |
|
73,6 → 74,14 |
gdt_p = (descriptor_t *) cpugdtr.base; |
gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits) - 1); |
gdtr_load(&cpugdtr); |
|
/* |
* Before we load new TSS limit, the current TSS descriptor |
* type must be changed to describe inactive TSS. |
*/ |
tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES]; |
tss_desc->type = AR_TSS; |
tr_load(gdtselector(TSS_DES)); |
} |
|
/** Perform amd64 specific tasks needed before the new thread is scheduled. */ |