2,14 → 2,14 |
<appendix id="archspecs"> |
<?dbhtml filename="arch.html"?> |
|
<title>Architecture Specific Notes</title> |
<title>Architecture specific notes</title> |
|
<section> |
<title>AMD64/Intel EM64T</title> |
|
<para>The amd64 architecture is a 64-bit extension of the older ia32 |
<para>The AMD64 architecture is a 64-bit extension of the older IA-32 |
architecture. Only 64-bit applications are supported. Creating this port |
was relatively easy, because it shares a lot of common code with ia32 |
was relatively easy, because it shares a lot of common code with IA-32 |
platform. However, the 64-bit extension has some specifics, which made the |
porting interesting.</para> |
|
16,7 → 16,7 |
<section> |
<title>Virtual Memory</title> |
|
<para>The amd64 architecture uses standard processor defined 4-level |
<para>The AMD64 architecture uses standard processor defined 4-level |
page mapping of 4KB pages. The NX(no-execute) flag on individual pages |
is fully supported.</para> |
</section> |
24,7 → 24,7 |
<section> |
<title>TLB-only Paging</title> |
|
<para>All memory on the amd64 architecture is memory mapped, if the |
<para>All memory on the AMD64 architecture is memory mapped, if the |
kernel needs to access physical memory, a mapping must be created. |
During boot process the boot loader creates mapping for the first 20MB |
of physical memory. To correctly initialize the page mapping system, an |
46,7 → 46,7 |
<section> |
<title>Mapping of Physical Memory</title> |
|
<para>The amd64 ABI document describes several modes of program layout. |
<para>The AMD64 ABI document describes several modes of program layout. |
The operating system kernel should be compiled in a |
<emphasis>kernel</emphasis> mode - the kernel is located in the negative |
2 gigabytes (0xffffffff80000000-0xfffffffffffffffff) and can access data |
71,13 → 71,13 |
<title>Fast SYSCALL/SYSRET Support</title> |
|
<para>The entry point for system calls was traditionally a speed problem |
on the ia32 architecture. The amd64 supports SYSCALL/SYSRET |
instructions. Upon encountering the SYSCALL instruction, the processor |
changes privilege mode and transfers control to an address stored in |
machine specific register. Unlike other similar instructions it does not |
change stack to a known kernel stack, which must be done by the syscall |
entry routine. A hidden part of a GS register is provided to support the |
entry routine with data needed for switching to kernel stack.</para> |
on IA32 architecture. AMD64 supports a SYSCALL/SYSRET instructions. Upon |
encountering SYSCALL instruction, the processor changes privilege mode |
and transfers control to an address stored in machine specific register. |
Unlike other similar instructions it does not change stack to a known |
kernel stack, which must be done by the syscall entry routine. A hidden |
part of a GS register is provided to support the entry routine with data |
needed for switching to kernel stack.</para> |
</section> |
|
<section> |
93,31 → 93,30 |
</section> |
|
<section> |
<title>Intel IA-32</title> |
<title>Intel IA32</title> |
|
<para>The ia32 architecture uses 4K pages and processor supported 2-level |
page tables. Along with amd64 It is one of the 2 architectures that fully |
supports SMP configurations. The architecture is mostly similar to amd64, |
it even shares a lot of code. The debugging support is the same as with |
amd64. The thread local storage uses GS register.</para> |
<para>The IA32 architecture uses 4K pages and processor supported 2-level |
page tables. Along with AMD64 It is one of the 2 architectures that fully |
supports SMP configurations. IA32 is mostly similar to AMD64, it even |
shares a lot of code. The debugging support is the same as with AMD64. The |
thread local storage uses GS register.</para> |
</section> |
|
<section> |
<title>32-bit MIPS</title> |
<title>MIPS32</title> |
|
<para>Both little and big endian kernels are supported. In order to test |
different page sizes, the mips32 page size was set to 16K. The mips32 |
architecture is TLB-only, the kernel simulates 2-level page tables. On |
processors that support it, lazy FPU context switching is |
implemented.</para> |
different page size it was set to 16K. The MIPS architecture is TLB-only, |
the kernel simulates 2-level page tables. On processors that support it, |
lazy FPU context switching is implemented.</para> |
|
<section> |
<title>Thread Local Storage</title> |
|
<para>The thread local storage support in compilers is a relatively |
recent phenomena. The standardization of such support for the mips32 |
platform is very new and even the newest versions of GCC cannot generate |
100% correct code. Because of some weird MIPS processor variants, it was |
recent phenomena. The standardization of such support for MIPS platform |
is very new and even the newest versions of GCC cannot generate 100% |
correct code. Because of some weird MIPS processor variants, it was |
decided, that the TLS pointer will be gathered not from some of the free |
registers, but a special instruction was devised and the kernel is |
supposed to emulate it. HelenOS expects that the TLS pointer is in the |