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• This comparison shows the changes necessary to convert path

  → /branches/tracing/kernel/arch @ 4393

  → /branches/tracing/kernel/arch @ 4692

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

No changes between revisions

Ignore whitespace Rev 4393 → Rev 4692

/branches/tracing/kernel/arch/sparc64/include/byteorder.h
File deleted

/branches/tracing/kernel/arch/sparc64/include/types.h
46,8 → 46,6
typedef unsigned long uint64_t;
typedef uint64_t size_t;
typedef uint64_t count_t;
typedef uint64_t index_t;
typedef uint64_t uintptr_t;
typedef uint64_t pfn_t;
60,11 → 58,9
typedef struct {
} fncptr_t;
/**< Formats for uintptr_t, size_t, count_t and index_t */
/**< Formats for uintptr_t, size_t */
#define PRIp "llx"
#define PRIs "llu"
#define PRIc "llu"
#define PRIi "llu"
/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
#define PRId8 "d"

/branches/tracing/kernel/arch/sparc64/include/atomic.h
123,7 → 123,7
"ldx %0, %2\n"
"brz %2, 0b\n"
"nop\n"
"ba %xcc, 1b\n"
"ba %%xcc, 1b\n"
"nop\n"
"2:\n"
: "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)

/branches/tracing/kernel/arch/sparc64/include/mm/tlb.h
322,7 → 322,7
* @return Current value of specified IMMU TLB Data Access
* Register.
*/
static inline uint64_t itlb_data_access_read(index_t entry)
static inline uint64_t itlb_data_access_read(size_t entry)
{
itlb_data_access_addr_t reg;
336,7 → 336,7
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void itlb_data_access_write(index_t entry, uint64_t value)
static inline void itlb_data_access_write(size_t entry, uint64_t value)
{
itlb_data_access_addr_t reg;
353,7 → 353,7
* @return Current value of specified DMMU TLB Data Access
* Register.
*/
static inline uint64_t dtlb_data_access_read(index_t entry)
static inline uint64_t dtlb_data_access_read(size_t entry)
{
dtlb_data_access_addr_t reg;
367,7 → 367,7
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
static inline void dtlb_data_access_write(size_t entry, uint64_t value)
{
dtlb_data_access_addr_t reg;
383,7 → 383,7
*
* @return Current value of specified IMMU TLB Tag Read Register.
*/
static inline uint64_t itlb_tag_read_read(index_t entry)
static inline uint64_t itlb_tag_read_read(size_t entry)
{
itlb_tag_read_addr_t tag;
398,7 → 398,7
*
* @return Current value of specified DMMU TLB Tag Read Register.
*/
static inline uint64_t dtlb_tag_read_read(index_t entry)
static inline uint64_t dtlb_tag_read_read(size_t entry)
{
dtlb_tag_read_addr_t tag;
418,7 → 418,7
* @return Current value of specified IMMU TLB Data Access
* Register.
*/
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
{
itlb_data_access_addr_t reg;
433,7 → 433,7
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void itlb_data_access_write(int tlb, index_t entry,
static inline void itlb_data_access_write(int tlb, size_t entry,
uint64_t value)
{
itlb_data_access_addr_t reg;
453,7 → 453,7
* @return Current value of specified DMMU TLB Data Access
* Register.
*/
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
{
dtlb_data_access_addr_t reg;
469,7 → 469,7
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void dtlb_data_access_write(int tlb, index_t entry,
static inline void dtlb_data_access_write(int tlb, size_t entry,
uint64_t value)
{
dtlb_data_access_addr_t reg;
488,7 → 488,7
*
* @return Current value of specified IMMU TLB Tag Read Register.
*/
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
{
itlb_tag_read_addr_t tag;
505,7 → 505,7
*
* @return Current value of specified DMMU TLB Tag Read Register.
*/
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
{
dtlb_tag_read_addr_t tag;

/branches/tracing/kernel/arch/sparc64/include/mm/tsb.h
160,9 → 160,9
struct as;
struct pte;
extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages);
extern void itsb_pte_copy(struct pte *t, index_t index);
extern void dtsb_pte_copy(struct pte *t, index_t index, bool ro);
extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages);
extern void itsb_pte_copy(struct pte *t, size_t index);
extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro);
#endif /* !def __ASM__ */

/branches/tracing/kernel/arch/sparc64/include/context.h
39,7 → 39,7
#include <arch/types.h>
#include <align.h>
#define SP_DELTA STACK_WINDOW_SAVE_AREA_SIZE
#define SP_DELTA (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE)
#ifdef context_set
#undef context_set

/branches/tracing/kernel/arch/sparc64/Makefile.inc
40,7 → 40,8
LFLAGS += -no-check-sections -N
DEFS += -D__64_BITS__
BITS = 64
ENDIANESS = BE
ifeq ($(PROCESSOR),us)
DEFS += -DUS

/branches/tracing/kernel/arch/sparc64/src/smp/smp.c
61,7 → 61,7
void smp_init(void)
{
ofw_tree_node_t *node;
count_t cnt = 0;
size_t cnt = 0;
if (is_us() || is_us_iii()) {
node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");

/branches/tracing/kernel/arch/sparc64/src/asm.S
277,7 → 277,7
*/
.global switch_to_userspace
switch_to_userspace:
save %o1, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
flushw
wrpr %g0, 0, %cleanwin ! avoid information leak

/branches/tracing/kernel/arch/sparc64/src/mm/tlb.c
54,8 → 54,8
#include <arch/mm/tsb.h>
#endif
static void dtlb_pte_copy(pte_t *, index_t, bool);
static void itlb_pte_copy(pte_t *, index_t);
static void dtlb_pte_copy(pte_t *, size_t, bool);
static void itlb_pte_copy(pte_t *, size_t);
static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
const char *);
130,7 → 130,7
* @param ro If true, the entry will be created read-only, regardless
* of its w field.
*/
void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
void dtlb_pte_copy(pte_t *t, size_t index, bool ro)
{
tlb_tag_access_reg_t tag;
tlb_data_t data;
167,7 → 167,7
* @param t Page Table Entry to be copied.
* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
*/
void itlb_pte_copy(pte_t *t, index_t index)
void itlb_pte_copy(pte_t *t, size_t index)
{
tlb_tag_access_reg_t tag;
tlb_data_t data;
200,7 → 200,7
void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
{
uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
size_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
pte_t *t;
page_table_lock(AS, true);
245,7 → 245,7
{
uintptr_t page_8k;
uintptr_t page_16k;
index_t index;
size_t index;
pte_t *t;
page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH;
309,7 → 309,7
void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
{
uintptr_t page_16k;
index_t index;
size_t index;
pte_t *t;
page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
497,38 → 497,7
dtlb_sfsr_write(0);
}
#if defined (US3)
/** Invalidates given TLB entry if and only if it is non-locked or global.
*
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1,
* TLB_ISMALL, TLB_IBIG).
* @param entry Entry index within the given TLB.
*/
static void tlb_invalidate_entry(int tlb, index_t entry)
{
tlb_data_t d;
tlb_tag_read_reg_t t;
if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) {
d.value = dtlb_data_access_read(tlb, entry);
if (!d.l || d.g) {
t.value = dtlb_tag_read_read(tlb, entry);
d.v = false;
dtlb_tag_access_write(t.value);
dtlb_data_access_write(tlb, entry, d.value);
}
} else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) {
d.value = itlb_data_access_read(tlb, entry);
if (!d.l || d.g) {
t.value = itlb_tag_read_read(tlb, entry);
d.v = false;
itlb_tag_access_write(t.value);
itlb_data_access_write(tlb, entry, d.value);
}
}
}
#endif
#if defined (US)
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
543,7 → 512,6
* be safe to invalidate them as late as now.
*/
#if defined (US)
tlb_data_t d;
tlb_tag_read_reg_t t;
567,22 → 535,19
}
}
}
#elif defined (US3)
for (i = 0; i < tlb_ismall_size(); i++)
tlb_invalidate_entry(TLB_ISMALL, i);
for (i = 0; i < tlb_ibig_size(); i++)
tlb_invalidate_entry(TLB_IBIG, i);
for (i = 0; i < tlb_dsmall_size(); i++)
tlb_invalidate_entry(TLB_DSMALL, i);
for (i = 0; i < tlb_dbig_size(); i++)
tlb_invalidate_entry(TLB_DBIG_0, i);
for (i = 0; i < tlb_dbig_size(); i++)
tlb_invalidate_entry(TLB_DBIG_1, i);
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
itlb_demap(TLB_DEMAP_ALL, 0, 0);
dtlb_demap(TLB_DEMAP_ALL, 0, 0);
}
#endif
}
/** Invalidate all ITLB and DTLB entries that belong to specified ASID
* (Context).
*
614,7 → 579,7
* @param page First page which to sweep out from ITLB and DTLB.
* @param cnt Number of ITLB and DTLB entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
{
unsigned int i;
tlb_context_reg_t pc_save, ctx;

/branches/tracing/kernel/arch/sparc64/src/mm/as.c
89,7 → 89,7
* The count must be calculated with respect to the emualted 16K page
* size.
*/
count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
size_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
sizeof(tsb_entry_t)) >> FRAME_WIDTH;
frame_free(KA2PA((uintptr_t) as->arch.itsb));
return cnt;
101,7 → 101,7
int as_create_arch(as_t *as, int flags)
{
#ifdef CONFIG_TSB
tsb_invalidate(as, 0, (count_t) -1);
tsb_invalidate(as, 0, (size_t) -1);
#endif
return 0;
}

/branches/tracing/kernel/arch/sparc64/src/mm/tsb.c
50,13 → 50,14
*
* @param as Address space.
* @param page First page to invalidate in TSB.
* @param pages Number of pages to invalidate. Value of (count_t) -1 means the
* @param pages Number of pages to invalidate. Value of (size_t) -1 means the
* whole TSB.
*/
void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
void tsb_invalidate(as_t *as, uintptr_t page, size_t pages)
{
index_t i0, i;
count_t cnt;
size_t i0;
size_t i;
size_t cnt;
ASSERT(as->arch.itsb && as->arch.dtsb);
63,7 → 64,7
i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
cnt = ITSB_ENTRY_COUNT;
else
cnt = pages * 2;
81,11 → 82,11
* @param t Software PTE.
* @param index Zero if lower 8K-subpage, one if higher 8K subpage.
*/
void itsb_pte_copy(pte_t *t, index_t index)
void itsb_pte_copy(pte_t *t, size_t index)
{
as_t *as;
tsb_entry_t *tsb;
index_t entry;
size_t entry;
ASSERT(index <= 1);
127,11 → 128,11
* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
* @param ro If true, the mapping is copied read-only.
*/
void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
void dtsb_pte_copy(pte_t *t, size_t index, bool ro)
{
as_t *as;
tsb_entry_t *tsb;
index_t entry;
size_t entry;
ASSERT(index <= 1);

/branches/tracing/kernel/arch/sparc64/src/drivers/fhc.c
71,7 → 71,7
if (!prop || !prop->value)
return NULL;
count_t regs = prop->size / sizeof(ofw_central_reg_t);
size_t regs = prop->size / sizeof(ofw_central_reg_t);
if (regs + 1 < UART_IMAP_REG)
return NULL;

/branches/tracing/kernel/arch/sparc64/src/drivers/scr.c
133,11 → 133,11
break;
case 16:
fb_scanline = fb_linebytes * (fb_depth >> 3);
visual = VISUAL_RGB_5_6_5;
visual = VISUAL_RGB_5_6_5_BE;
break;
case 24:
fb_scanline = fb_linebytes * 4;
visual = VISUAL_RGB_8_8_8_0;
visual = VISUAL_BGR_8_8_8_0;
break;
case 32:
fb_scanline = fb_linebytes * (fb_depth >> 3);
177,11 → 177,11
break;
case 16:
fb_scanline = fb_linebytes * (fb_depth >> 3);
visual = VISUAL_RGB_5_6_5;
visual = VISUAL_RGB_5_6_5_BE;
break;
case 24:
fb_scanline = fb_linebytes * 4;
visual = VISUAL_RGB_8_8_8_0;
visual = VISUAL_BGR_8_8_8_0;
break;
case 32:
fb_scanline = fb_linebytes * (fb_depth >> 3);

/branches/tracing/kernel/arch/sparc64/src/drivers/pci.c
91,7 → 91,7
return NULL;
ofw_upa_reg_t *reg = prop->value;
count_t regs = prop->size / sizeof(ofw_upa_reg_t);
size_t regs = prop->size / sizeof(ofw_upa_reg_t);
if (regs < SABRE_INTERNAL_REG + 1)
return NULL;
138,7 → 138,7
return NULL;
ofw_upa_reg_t *reg = prop->value;
count_t regs = prop->size / sizeof(ofw_upa_reg_t);
size_t regs = prop->size / sizeof(ofw_upa_reg_t);
if (regs < PSYCHO_INTERNAL_REG + 1)
return NULL;

/branches/tracing/kernel/arch/ia64/include/byteorder.h
File deleted

/branches/tracing/kernel/arch/ia64/include/types.h
54,8 → 54,6
} uint128_t;
typedef uint64_t size_t;
typedef uint64_t count_t;
typedef uint64_t index_t;
typedef uint64_t uintptr_t;
typedef uint64_t pfn_t;
72,8 → 70,6
#define PRIp "lx" /**< Format for uintptr_t. */
#define PRIs "lu" /**< Format for size_t. */
#define PRIc "lu" /**< Format for count_t. */
#define PRIi "lu" /**< Format for index_t. */
#define PRId8 "d" /**< Format for int8_t. */
#define PRId16 "d" /**< Format for int16_t. */

/branches/tracing/kernel/arch/ia64/include/atomic.h
52,12 → 52,12
return v;
}
static inline uint64_t test_and_set(atomic_t *val) {
static inline uint64_t test_and_set(atomic_t *val)
{
uint64_t v;
asm volatile (
"movl %0 = 0x01;;\n"
"movl %0 = 0x1;;\n"
"xchg8 %0 = %1, %0;;\n"
: "=r" (v), "+m" (val->count)
);
65,6 → 65,13
return v;
}
static inline void atomic_lock_arch(atomic_t *val)
{
do {
while (val->count)
;
} while (test_and_set(val));
}
static inline void atomic_inc(atomic_t *val)
{

/branches/tracing/kernel/arch/ia64/include/mm/page.h
240,7 → 240,7
*
* @return Current contents of rr[i].
*/
static inline uint64_t rr_read(index_t i)
static inline uint64_t rr_read(size_t i)
{
uint64_t ret;
ASSERT(i < REGION_REGISTERS);
253,7 → 253,7
* @param i Region register index.
* @param v Value to be written to rr[i].
*/
static inline void rr_write(index_t i, uint64_t v)
static inline void rr_write(size_t i, uint64_t v)
{
ASSERT(i < REGION_REGISTERS);
asm volatile (

/branches/tracing/kernel/arch/ia64/include/mm/tlb.h
76,12 → 76,12
extern void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry);
extern void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry);
extern void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr);
extern void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr);
extern void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr);
extern void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, size_t tr);
extern void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr);
extern void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr);
extern void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr);
extern void dtr_purge(uintptr_t page, count_t width);
extern void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, size_t tr);
extern void dtr_purge(uintptr_t page, size_t width);
extern void dtc_pte_copy(pte_t *t);
extern void itc_pte_copy(pte_t *t);
92,6 → 92,7
extern void data_dirty_bit_fault(uint64_t vector, istate_t *istate);
extern void instruction_access_bit_fault(uint64_t vector, istate_t *istate);
extern void data_access_bit_fault(uint64_t vector, istate_t *istate);
extern void data_access_rights_fault(uint64_t vector, istate_t *istate);
extern void page_not_present(uint64_t vector, istate_t *istate);
#endif

/branches/tracing/kernel/arch/ia64/Makefile.inc
41,7 → 41,8
LFLAGS += -EL
AFLAGS += -mconstant-gp
DEFS += -D__64_BITS__
BITS = 64
ENDIANESS = LE
ARCH_SOURCES = \
arch/$(KARCH)/src/start.S \

/branches/tracing/kernel/arch/ia64/src/ivt.S
536,7 → 536,7
HEAVYWEIGHT_HANDLER 0x5000 page_not_present
HEAVYWEIGHT_HANDLER 0x5100
HEAVYWEIGHT_HANDLER 0x5200
HEAVYWEIGHT_HANDLER 0x5300
HEAVYWEIGHT_HANDLER 0x5300 data_access_rights_fault
HEAVYWEIGHT_HANDLER 0x5400 general_exception
HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
HEAVYWEIGHT_HANDLER 0x5600

/branches/tracing/kernel/arch/ia64/src/mm/tlb.c
100,7 → 100,7
}
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
{
region_register rr;
bool restore_rr = false;
267,7 → 267,7
* @param tr Translation register.
*/
void
itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
{
tr_mapping_insert(va, asid, entry, false, tr);
}
281,7 → 281,7
* @param tr Translation register.
*/
void
dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
{
tr_mapping_insert(va, asid, entry, true, tr);
}
298,7 → 298,7
*/
void
tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
index_t tr)
size_t tr)
{
region_register rr;
bool restore_rr = false;
353,7 → 353,7
*/
void
dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
index_t tr)
size_t tr)
{
tlb_entry_t entry;
382,7 → 382,7
* @param page Virtual page address including VRN bits.
* @param width Width of the purge in bits.
*/
void dtr_purge(uintptr_t page, count_t width)
void dtr_purge(uintptr_t page, size_t width)
{
asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
}
710,6 → 710,37
page_table_unlock(AS, true);
}
/** Data access rights fault handler.
*
* @param vector Interruption vector.
* @param istate Structure with saved interruption state.
*/
void data_access_rights_fault(uint64_t vector, istate_t *istate)
{
region_register rr;
rid_t rid;
uintptr_t va;
pte_t *t;
va = istate->cr_ifa; /* faulting address */
rr.word = rr_read(VA2VRN(va));
rid = rr.map.rid;
/*
* Assume a write to a read-only page.
*/
page_table_lock(AS, true);
t = page_mapping_find(AS, va);
ASSERT(t && t->p);
ASSERT(!t->w);
if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
fault_if_from_uspace(istate, "Page fault at %p.", va);
panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
istate->cr_iip);
}
page_table_unlock(AS, true);
}
/** Page not present fault handler.
*
* @param vector Interruption vector.

/branches/tracing/kernel/arch/ia64/src/mm/vhpt.c
53,7 → 53,7
void vhpt_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
{
region_register rr_save, rr;
index_t vrn;
size_t vrn;
rid_t rid;
uint64_t tag;

/branches/tracing/kernel/arch/ia64/src/mm/page.c
131,7 → 131,7
vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
{
region_register rr_save, rr;
index_t vrn;
size_t vrn;
rid_t rid;
vhpt_entry_t *v;
176,7 → 176,7
bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
{
region_register rr_save, rr;
index_t vrn;
size_t vrn;
rid_t rid;
bool match;
223,7 → 223,7
int flags)
{
region_register rr_save, rr;
index_t vrn;
size_t vrn;
rid_t rid;
uint64_t tag;

/branches/tracing/kernel/arch/arm32/include/byteorder.h
File deleted

/branches/tracing/kernel/arch/arm32/include/exception.h
136,6 → 136,13
extern void install_exception_handlers(void);
extern void exception_init(void);
extern void print_istate(istate_t *istate);
extern void reset_exception_entry(void);
extern void irq_exception_entry(void);
extern void fiq_exception_entry(void);
extern void undef_instr_exception_entry(void);
extern void prefetch_abort_exception_entry(void);
extern void data_abort_exception_entry(void);
extern void swi_exception_entry(void);
#endif

/branches/tracing/kernel/arch/arm32/include/types.h
53,8 → 53,6
typedef unsigned long long uint64_t;
typedef uint32_t size_t;
typedef uint32_t count_t;
typedef uint32_t index_t;
typedef uint32_t uintptr_t;
typedef uint32_t pfn_t;
69,8 → 67,6
#define PRIp "x" /**< Format for uintptr_t. */
#define PRIs "u" /**< Format for size_t. */
#define PRIc "u" /**< Format for count_t. */
#define PRIi "u" /**< Format for index_t. */
#define PRId8 "d" /**< Format for int8_t. */
#define PRId16 "d" /**< Format for int16_t. */

/branches/tracing/kernel/arch/arm32/include/machine_func.h
0,0 → 1,132
/*
* Copyright (c) 2007 Michal Kebrt
* Copyright (c) 2009 Vineeth Pillai
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup arm32
* @{
*/
/** @file
* @brief Declarations of machine specific functions.
*
* These functions enable to differentiate more kinds of ARM emulators
* or CPUs. It's the same concept as "arch" functions on the architecture
* level.
*/
#ifndef KERN_arm32_MACHINE_FUNC_H_
#define KERN_arm32_MACHINE_FUNC_H_
#include <console/console.h>
#include <arch/types.h>
#include <arch/exception.h>
#define MACHINE_GENFUNC machine_genfunc
struct arm_machine_ops {
void (*machine_grab_console)(void);
void (*machine_release_console)(void);
void (*machine_init)(void);
void (*machine_timer_irq_start)(void);
void (*machine_cpu_halt)(void);
uintptr_t (*machine_get_memory_size)(void);
void (*machine_fb_init)(void);
void (*machine_irq_exception)(int, istate_t*);
uintptr_t (*machine_get_fb_address)(void);
void (*machine_frame_init)(void);
void (*machine_output_init)(void);
void (*machine_input_init)(void);
};
extern struct arm_machine_ops machine_ops;
/** Acquire console back for kernel. */
extern void machine_grab_console(void);
/** Return console to userspace. */
extern void machine_release_console(void);
/** Maps HW devices to the kernel address space using #hw_map. */
extern void machine_init(void);
/** Starts timer. */
extern void machine_timer_irq_start(void);
/** Halts CPU. */
extern void machine_cpu_halt(void);
/** Returns size of available memory.
*
* @return Size of available memory.
*/
extern uintptr_t machine_get_memory_size(void);
/** Initializes the Frame Buffer
*
*/
extern void machine_fb_init(void);
/** Interrupt exception handler.
*
* @param exc_no Interrupt exception number.
* @param istate Saved processor state.
*/
extern void machine_irq_exception(int exc_no, istate_t *istate);
/** Returns address of framebuffer device.
*
* @return Address of framebuffer device.
*/
extern uintptr_t machine_get_fb_address(void);
/*
* Machine specific frame initialization
*/
extern void machine_frame_init(void);
/*
* configure the serial line output device.
*/
extern void machine_output_init(void);
/*
* configure the serial line input device.
*/
extern void machine_input_init(void);
extern void machine_genfunc(void);
#endif
/** @}
*/

/branches/tracing/kernel/arch/arm32/include/mach/testarm/testarm.h
0,0 → 1,87
/*
* Copyright (c) 2007 Michal Kebrt
* Copyright (c) 2009 Vineeth Pillai
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup arm32gxemul GXemul
* @brief GXemul machine specific parts.
* @ingroup arm32
* @{
*/
/** @file
* @brief GXemul peripheries drivers declarations.
*/
#ifndef KERN_arm32_MACHINE_H_
#define KERN_arm32_MACHINE_H_
#include <arch/machine_func.h>
/** Last interrupt number (beginning from 0) whose status is probed
* from interrupt controller
*/
#define GXEMUL_IRQC_MAX_IRQ 8
#define GXEMUL_KBD_IRQ 2
#define GXEMUL_TIMER_IRQ 4
/** Timer frequency */
#define GXEMUL_TIMER_FREQ 100
#define GXEMUL_KBD_ADDRESS 0x10000000
#define GXEMUL_MP_ADDRESS 0x11000000
#define GXEMUL_FB_ADDRESS 0x12000000
#define GXEMUL_RTC_ADDRESS 0x15000000
#define GXEMUL_IRQC_ADDRESS 0x16000000
extern void *gxemul_kbd;
extern void *gxemul_rtc;
extern void *gxemul_irqc;
#define GXEMUL_HALT_OFFSET 0x010
#define GXEMUL_RTC_FREQ_OFFSET 0x100
#define GXEMUL_MP_MEMSIZE_OFFSET 0x090
#define GXEMUL_RTC_ACK_OFFSET 0x110
extern void gxemul_init(void);
extern void gxemul_fb_init(void);
extern void gxemul_output_init(void);
extern void gxemul_input_init(void);
extern void gxemul_release_console(void);
extern void gxemul_grab_console(void);
extern void gxemul_timer_irq_start(void);
extern void gxemul_cpu_halt(void);
extern void gxemul_irq_exception(int exc_no, istate_t *istate);
extern uintptr_t gxemul_get_memory_size(void);
extern uintptr_t gxemul_get_fb_address(void);
extern void gxemul_fb_init(void);
extern void gxemul_frame_init(void);
#endif
/** @}
*/

/branches/tracing/kernel/arch/arm32/include/mach/integratorcp/integratorcp.h
0,0 → 1,116
/*
* Copyright (c) 2009 Vineeth Pillai
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup arm32integratorcp
* @brief Integratorcp machine specific parts.
* @ingroup arm32
* @{
*/
/** @file
* @brief Integratorcp peripheries drivers declarations.
*/
#ifndef KERN_arm32_MACHINE_H_
#define KERN_arm32_MACHINE_H_
#include <arch/machine_func.h>
/** Last interrupt number (beginning from 0) whose status is probed
* from interrupt controller
*/
#define ICP_IRQC_MAX_IRQ 8
#define ICP_KBD_IRQ 3
#define ICP_TIMER_IRQ 6
/** Timer frequency */
#define ICP_TIMER_FREQ 10000
#define ICP_UART 0x16000000
#define ICP_KBD 0x18000000
#define ICP_KBD_STAT 0x04
#define ICP_KBD_DATA 0x08
#define ICP_KBD_INTR_STAT 0x10
#define ICP_RTC 0x13000000
#define ICP_RTC1_LOAD_OFFSET 0x100
#define ICP_RTC1_READ_OFFSET 0x104
#define ICP_RTC1_CTL_OFFSET 0x108
#define ICP_RTC1_INTRCLR_OFFSET 0x10C
#define ICP_RTC1_INTRSTAT_OFFSET 0x114
#define ICP_RTC1_BGLOAD_OFFSET 0x118
#define ICP_RTC_CTL_VALUE 0x00E2
#define ICP_IRQC 0x14000000
#define ICP_IRQC_MASK_OFFSET 0xC
#define ICP_IRQC_UNMASK_OFFSET 0x8
#define ICP_FB 0x00800000
#define ICP_FB_FRAME (ICP_FB >> 12)
#define ICP_FB_NUM_FRAME 512
#define ICP_VGA 0xC0000000
#define ICP_CMCR 0x10000000
#define ICP_SDRAM_MASK 0x1C
#define ICP_SDRAMCR_OFFSET 0x20
typedef struct {
uintptr_t uart;
uintptr_t kbd_ctrl;
uintptr_t kbd_stat;
uintptr_t kbd_data;
uintptr_t kbd_intstat;
uintptr_t rtc;
uintptr_t rtc1_load;
uintptr_t rtc1_read;
uintptr_t rtc1_ctl;
uintptr_t rtc1_intrclr;
uintptr_t rtc1_intrstat;
uintptr_t rtc1_bgload;
uintptr_t irqc;
uintptr_t irqc_mask;
uintptr_t irqc_unmask;
uintptr_t vga;
uintptr_t cmcr;
uintptr_t sdramcr;
} icp_hw_map_t;
extern void icp_init(void);
extern void icp_fb_init(void);
extern void icp_output_init(void);
extern void icp_input_init(void);
extern void icp_release_console(void);
extern void icp_grab_console(void);
extern void icp_timer_irq_start(void);
extern void icp_cpu_halt(void);
extern void icp_irq_exception(int exc_no, istate_t *istate);
extern uintptr_t icp_get_memory_size(void);
extern uintptr_t icp_get_fb_address(void);
extern void icp_fb_init(void);
extern void icp_frame_init(void);
#endif
/** @}
*/

/branches/tracing/kernel/arch/arm32/include/mm/page.h
94,21 → 94,21
/* Get PTE flags accessors for each level. */
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i))
get_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i))
get_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i))
/* Set PTE flags accessors for each level. */
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x))
set_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x))
set_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i), (x))
/* Macros for querying the last-level PTE entries. */
#define PTE_VALID_ARCH(pte) \
204,7 → 204,7
* @param pt Level 0 page table.
* @param i Index of the entry to return.
*/
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
static inline int get_pt_level0_flags(pte_level0_t *pt, size_t i)
{
pte_level0_t *p = &pt[i];
int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
219,7 → 219,7
* @param pt Level 1 page table.
* @param i Index of the entry to return.
*/
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
static inline int get_pt_level1_flags(pte_level1_t *pt, size_t i)
{
pte_level1_t *p = &pt[i];
244,7 → 244,7
* @param i index of the entry to be changed
* @param flags new flags
*/
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
static inline void set_pt_level0_flags(pte_level0_t *pt, size_t i, int flags)
{
pte_level0_t *p = &pt[i];
272,7 → 272,7
* @param i Index of the entry to be changed.
* @param flags New flags.
*/
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
static inline void set_pt_level1_flags(pte_level1_t *pt, size_t i, int flags)
{
pte_level1_t *p = &pt[i];

/branches/tracing/kernel/arch/arm32/include/drivers/gxemul.h
File deleted

/branches/tracing/kernel/arch/arm32/Makefile.inc
39,12 → 39,15
GCC_CFLAGS += -fno-zero-initialized-in-bss
DEFS += -D__32_BITS__
BITS = 32
ENDIANESS = LE
ARCH_SOURCES = \
arch/$(KARCH)/src/start.S \
arch/$(KARCH)/src/asm.S \
arch/$(KARCH)/src/exc_handler.S \
arch/$(KARCH)/src/arm32.c \
arch/$(KARCH)/src/machine_func.c \
arch/$(KARCH)/src/context.S \
arch/$(KARCH)/src/dummy.S \
arch/$(KARCH)/src/panic.S \
57,5 → 60,16
arch/$(KARCH)/src/mm/frame.c \
arch/$(KARCH)/src/mm/page.c \
arch/$(KARCH)/src/mm/tlb.c \
arch/$(KARCH)/src/mm/page_fault.c \
arch/$(KARCH)/src/drivers/gxemul.c
arch/$(KARCH)/src/mm/page_fault.c
ifeq ($(MACHINE),testarm)
ARCH_SOURCES += arch/$(KARCH)/src/mach/testarm/testarm.c
endif
ifeq ($(MACHINE),integratorcp)
ARCH_SOURCES += arch/$(KARCH)/src/mach/integratorcp/integratorcp.c
endif
ifeq ($(CONFIG_PL050),y)
ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c
endif

/branches/tracing/kernel/arch/arm32/src/exception.c
39,11 → 39,18
#include <interrupt.h>
#include <arch/mm/page_fault.h>
#include <arch/barrier.h>
#include <arch/drivers/gxemul.h>
#include <print.h>
#include <syscall/syscall.h>
#include <udebug/udebug.h>
#ifdef MACHINE_testarm
#include <arch/mach/testarm/testarm.h>
#endif
#ifdef MACHINE_integratorcp
#include <arch/mach/integratorcp/integratorcp.h>
#endif
/** Offset used in calculation of exception handler's relative address.
*
* @see install_handler()
59,159 → 66,6
/** Size of memory block occupied by exception vectors. */
#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)
/** Switches to kernel stack and saves all registers there.
*
* Temporary exception stack is used to save a few registers
* before stack switch takes place.
*
*/
inline static void setup_stack_and_save_regs()
{
asm volatile (
"ldr r13, =exc_stack\n"
"stmfd r13!, {r0}\n"
"mrs r0, spsr\n"
"and r0, r0, #0x1f\n"
"cmp r0, #0x10\n"
"bne 1f\n"
/* prev mode was usermode */
"ldmfd r13!, {r0}\n"
"ldr r13, =supervisor_sp\n"
"ldr r13, [r13]\n"
"stmfd r13!, {lr}\n"
"stmfd r13!, {r0-r12}\n"
"stmfd r13!, {r13, lr}^\n"
"mrs r0, spsr\n"
"stmfd r13!, {r0}\n"
"b 2f\n"
/* mode was not usermode */
"1:\n"
"stmfd r13!, {r1, r2, r3}\n"
"mrs r1, cpsr\n"
"mov r2, lr\n"
"bic r1, r1, #0x1f\n"
"orr r1, r1, r0\n"
"mrs r0, cpsr\n"
"msr cpsr_c, r1\n"
"mov r3, r13\n"
"stmfd r13!, {r2}\n"
"mov r2, lr\n"
"stmfd r13!, {r4-r12}\n"
"mov r1, r13\n"
/* the following two lines are for debugging */
"mov sp, #0\n"
"mov lr, #0\n"
"msr cpsr_c, r0\n"
"ldmfd r13!, {r4, r5, r6, r7}\n"
"stmfd r1!, {r4, r5, r6}\n"
"stmfd r1!, {r7}\n"
"stmfd r1!, {r2}\n"
"stmfd r1!, {r3}\n"
"mrs r0, spsr\n"
"stmfd r1!, {r0}\n"
"mov r13, r1\n"
"2:\n"
);
}
/** Returns from exception mode.
*
* Previously saved state of registers (including control register)
* is restored from the stack.
*/
inline static void load_regs()
{
asm volatile(
"ldmfd r13!, {r0} \n"
"msr spsr, r0 \n"
"and r0, r0, #0x1f \n"
"cmp r0, #0x10 \n"
"bne 1f \n"
/* return to user mode */
"ldmfd r13!, {r13, lr}^ \n"
"b 2f \n"
/* return to non-user mode */
"1:\n"
"ldmfd r13!, {r1, r2} \n"
"mrs r3, cpsr \n"
"bic r3, r3, #0x1f \n"
"orr r3, r3, r0 \n"
"mrs r0, cpsr \n"
"msr cpsr_c, r3 \n"
"mov r13, r1 \n"
"mov lr, r2 \n"
"msr cpsr_c, r0 \n"
/* actual return */
"2:\n"
"ldmfd r13, {r0-r12, pc}^\n"
);
}
/** Switch CPU to mode in which interrupts are serviced (currently it
* is Undefined mode).
*
* The default mode for interrupt servicing (Interrupt Mode)
* can not be used because of nested interrupts (which can occur
* because interrupts are enabled in higher levels of interrupt handler).
*/
inline static void switch_to_irq_servicing_mode()
{
/* switch to Undefined mode */
asm volatile(
/* save regs used during switching */
"stmfd sp!, {r0-r3} \n"
/* save stack pointer and link register to r1, r2 */
"mov r1, sp \n"
"mov r2, lr \n"
/* mode switch */
"mrs r0, cpsr \n"
"bic r0, r0, #0x1f \n"
"orr r0, r0, #0x1b \n"
"msr cpsr_c, r0 \n"
/* restore saved sp and lr */
"mov sp, r1 \n"
"mov lr, r2 \n"
/* restore original regs */
"ldmfd sp!, {r0-r3} \n"
);
}
/** Calls exception dispatch routine. */
#define CALL_EXC_DISPATCH(exception) \
asm volatile ( \
"mov r0, %[exc]\n" \
"mov r1, r13\n" \
"bl exc_dispatch\n" \
:: [exc] "i" (exception) \
);\
/** General exception handler.
*
* Stores registers, dispatches the exception,
* and finally restores registers and returns from exception processing.
*
* @param exception Exception number.
*/
#define PROCESS_EXCEPTION(exception) \
setup_stack_and_save_regs(); \
CALL_EXC_DISPATCH(exception) \
load_regs();
/** Updates specified exception vector to jump to given handler.
*
* Addresses of handlers are stored in memory following exception vectors.
233,71 → 87,6
}
/** Low-level Reset Exception handler. */
static void reset_exception_entry(void)
{
PROCESS_EXCEPTION(EXC_RESET);
}
/** Low-level Software Interrupt Exception handler. */
static void swi_exception_entry(void)
{
PROCESS_EXCEPTION(EXC_SWI);
}
/** Low-level Undefined Instruction Exception handler. */
static void undef_instr_exception_entry(void)
{
PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
/** Low-level Fast Interrupt Exception handler. */
static void fiq_exception_entry(void)
{
PROCESS_EXCEPTION(EXC_FIQ);
}
/** Low-level Prefetch Abort Exception handler. */
static void prefetch_abort_exception_entry(void)
{
asm volatile (
"sub lr, lr, #4"
);
PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
/** Low-level Data Abort Exception handler. */
static void data_abort_exception_entry(void)
{
asm volatile (
"sub lr, lr, #8"
);
PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
/** Low-level Interrupt Exception handler.
*
* CPU is switched to Undefined mode before further interrupt processing
* because of possible occurence of nested interrupt exception, which
* would overwrite (and thus spoil) stack pointer.
*/
static void irq_exception_entry(void)
{
asm volatile (
"sub lr, lr, #4"
);
setup_stack_and_save_regs();
switch_to_irq_servicing_mode();
CALL_EXC_DISPATCH(EXC_IRQ)
load_regs();
}
/** Software Interrupt handler.
*
* Dispatches the syscall.
308,37 → 97,6
istate->r3, istate->r4, istate->r5, istate->r6);
}
/** Returns the mask of active interrupts. */
static inline uint32_t gxemul_irqc_get_sources(void)
{
return *((uint32_t *) gxemul_irqc);
}
/** Interrupt Exception handler.
*
* Determines the sources of interrupt and calls their handlers.
*/
static void irq_exception(int exc_no, istate_t *istate)
{
uint32_t sources = gxemul_irqc_get_sources();
unsigned int i;
for (i = 0; i < GXEMUL_IRQC_MAX_IRQ; i++) {
if (sources & (1 << i)) {
irq_t *irq = irq_dispatch_and_lock(i);
if (irq) {
/* The IRQ handler was found. */
irq->handler(irq);
spinlock_unlock(&irq->lock);
} else {
/* Spurious interrupt.*/
printf("cpu%d: spurious interrupt (inum=%d)\n",
CPU->id, i);
}
}
}
}
/** Fills exception vectors with appropriate exception handlers. */
void install_exception_handlers(void)
{
385,6 → 143,15
}
#endif
/** Interrupt Exception handler.
*
* Determines the sources of interrupt and calls their handlers.
*/
static void irq_exception(int exc_no, istate_t *istate)
{
machine_irq_exception(exc_no, istate);
}
/** Initializes exception handling.
*
* Installs low-level exception handlers and then registers

/branches/tracing/kernel/arch/arm32/src/start.S
35,11 → 35,33
.global supervisor_sp
kernel_image_start:
# initialize Stack pointer for exception modes
mrs r4, cpsr
bic r4, r4, #0x1f
#FIQ Mode
orr r3, r4, #0x11
msr cpsr_c, r3
ldr sp, =exc_stack
#IRQ Mode
orr r3, r4, #0x12
msr cpsr_c, r3
ldr sp, =exc_stack
#ABORT Mode
orr r3, r4, #0x17
msr cpsr_c, r3
ldr sp, =exc_stack
#UNDEFINED Mode
orr r3, r4, #0x1b
msr cpsr_c, r3
ldr sp, =exc_stack
# switch to supervisor mode
mrs r3, cpsr
bic r3, r3, #0x1f
orr r3, r3, #0x13
orr r3, r4, #0x13
msr cpsr_c, r3
ldr sp, =temp_stack

/branches/tracing/kernel/arch/arm32/src/machine_func.c
0,0 → 1,147
/*
* Copyright (c) 2009 Vineeth Pillai
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup arm32
* @{
*/
/** @file
* @brief Definitions of machine specific functions.
*
* These functions enable to differentiate more kinds of ARM emulators
* or CPUs. It's the same concept as "arch" functions on the architecture
* level.
*/
#include <arch/machine_func.h>
/** Acquire console back for kernel. */
void machine_grab_console(void)
{
(machine_ops.machine_grab_console)();
}
/** Return console to userspace. */
void machine_release_console(void)
{
(machine_ops.machine_release_console)();
}
/** Maps HW devices to the kernel address space using #hw_map. */
void machine_init(void)
{
(machine_ops.machine_init)();
}
/** Starts timer. */
void machine_timer_irq_start(void)
{
(machine_ops.machine_timer_irq_start)();
}
/** Halts CPU. */
void machine_cpu_halt(void)
{
(machine_ops.machine_cpu_halt)();
}
/** Returns size of available memory.
*
* @return Size of available memory.
*/
uintptr_t machine_get_memory_size(void)
{
return (machine_ops.machine_get_memory_size)();
}
/** Initializes the Frame Buffer
*
*/
void machine_fb_init(void)
{
(machine_ops.machine_fb_init)();
}
/** Interrupt exception handler.
*
* @param exc_no Interrupt exception number.
* @param istate Saved processor state.
*/
void machine_irq_exception(int exc_no, istate_t *istate)
{
(machine_ops.machine_irq_exception)(exc_no, istate);
}
/** Returns address of framebuffer device.
*
* @return Address of framebuffer device.
*/
uintptr_t machine_get_fb_address(void)
{
return (machine_ops.machine_get_fb_address)();
}
/*
* Machine specific frame initialization
*/
void machine_frame_init(void)
{
(machine_ops.machine_frame_init)();
}
/*
* configure the output device.
*/
void machine_output_init(void)
{
(machine_ops.machine_output_init)();
}
/*
* configure the input device.
*/
void machine_input_init(void)
{
(machine_ops.machine_input_init)();
}
/*
* Generic function to use, if sepcific function doesn't define any of the above functions.
*/
void machine_genfunc()
{
}
/** @}
*/

/branches/tracing/kernel/arch/arm32/src/arm32.c
37,13 → 37,9
#include <config.h>
#include <genarch/fb/fb.h>
#include <genarch/fb/visuals.h>
#include <genarch/drivers/dsrln/dsrlnin.h>
#include <genarch/drivers/dsrln/dsrlnout.h>
#include <genarch/srln/srln.h>
#include <sysinfo/sysinfo.h>
#include <console/console.h>
#include <ddi/irq.h>
#include <arch/drivers/gxemul.h>
#include <print.h>
#include <config.h>
#include <interrupt.h>
52,6 → 48,15
#include <macros.h>
#include <string.h>
#ifdef MACHINE_testarm
#include <arch/mach/testarm/testarm.h>
#endif
#ifdef MACHINE_integratorcp
#include <arch/mach/integratorcp/integratorcp.h>
#endif
/** Performs arm32-specific initialization before main_bsp() is called. */
void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
{
77,7 → 82,7
/** Performs arm32 specific initialization afterr mm is initialized. */
void arch_post_mm_init(void)
{
gxemul_init();
machine_init();
/* Initialize exception dispatch table */
exception_init();
84,18 → 89,10
interrupt_init();
#ifdef CONFIG_FB
fb_properties_t prop = {
.addr = GXEMUL_FB_ADDRESS,
.offset = 0,
.x = 640,
.y = 480,
.scan = 1920,
.visual = VISUAL_BGR_8_8_8,
};
fb_init(&prop);
machine_fb_init();
#else
#ifdef CONFIG_ARM_PRN
dsrlnout_init((ioport8_t *) gxemul_kbd);
machine_output_init();
#endif /* CONFIG_ARM_PRN */
#endif /* CONFIG_FB */
}
126,30 → 123,7
*/
void arch_post_smp_init(void)
{
#ifdef CONFIG_ARM_KBD
/*
* Initialize the GXemul keyboard port. Then initialize the serial line
* module and connect it to the GXemul keyboard.
*/
dsrlnin_instance_t *dsrlnin_instance
= dsrlnin_init((dsrlnin_t *) gxemul_kbd, GXEMUL_KBD_IRQ);
if (dsrlnin_instance) {
srln_instance_t *srln_instance = srln_init();
if (srln_instance) {
indev_t *sink = stdin_wire();
indev_t *srln = srln_wire(srln_instance, sink);
dsrlnin_wire(dsrlnin_instance, srln);
}
}
/*
* This is the necessary evil until the userspace driver is entirely
* self-sufficient.
*/
sysinfo_set_item_val("kbd", NULL, true);
sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ);
sysinfo_set_item_val("kbd.address.virtual", NULL, (unative_t) gxemul_kbd);
#endif
machine_input_init();
}
156,7 → 130,6
/** Performs arm32 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
tlb_invalidate_all();
}
168,6 → 141,7
{
uint8_t *stck;
tlb_invalidate_all();
stck = &THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA];
supervisor_sp = (uintptr_t) stck;
}
183,8 → 157,7
/** Halts CPU. */
void cpu_halt(void)
{
*((char *) (gxemul_kbd + GXEMUL_HALT_OFFSET))
= 0;
machine_cpu_halt();
}
/** Reboot. */
211,6 → 184,7
/** Acquire console back for kernel. */
void arch_grab_console(void)
{
machine_grab_console();
#ifdef CONFIG_FB
fb_redraw();
#endif
219,6 → 193,7
/** Return console to userspace. */
void arch_release_console(void)
{
machine_release_console();
}
/** @}

/branches/tracing/kernel/arch/arm32/src/mach/testarm/testarm.c
0,0 → 1,242
/*
* Copyright (c) 2007 Michal Kebrt, Petr Stepan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup arm32gxemul
* @{
*/
/** @file
* @brief GXemul drivers.
*/
#include <arch/exception.h>
#include <arch/mach/testarm/testarm.h>
#include <mm/page.h>
#include <genarch/fb/fb.h>
#include <genarch/fb/visuals.h>
#include <genarch/drivers/dsrln/dsrlnin.h>
#include <genarch/drivers/dsrln/dsrlnout.h>
#include <genarch/srln/srln.h>
#include <console/console.h>
#include <ddi/irq.h>
#include <ddi/device.h>
#include <config.h>
#include <sysinfo/sysinfo.h>
#include <interrupt.h>
#include <print.h>
void *gxemul_kbd;
void *gxemul_rtc;
void *gxemul_irqc;
static irq_t gxemul_timer_irq;
struct arm_machine_ops machine_ops = {
MACHINE_GENFUNC,
MACHINE_GENFUNC,
gxemul_init,
gxemul_timer_irq_start,
gxemul_cpu_halt,
gxemul_get_memory_size,
gxemul_fb_init,
gxemul_irq_exception,
gxemul_get_fb_address,
gxemul_frame_init,
gxemul_output_init,
gxemul_input_init
};
void gxemul_init(void)
{
gxemul_kbd = (void *) hw_map(GXEMUL_KBD_ADDRESS, PAGE_SIZE);
gxemul_rtc = (void *) hw_map(GXEMUL_RTC_ADDRESS, PAGE_SIZE);
gxemul_irqc = (void *) hw_map(GXEMUL_IRQC_ADDRESS, PAGE_SIZE);
}
void gxemul_fb_init(void)
{
fb_properties_t prop = {
.addr = GXEMUL_FB_ADDRESS,
.offset = 0,
.x = 640,
.y = 480,
.scan = 1920,
.visual = VISUAL_RGB_8_8_8,
};
fb_init(&prop);
}
void gxemul_output_init(void)
{
dsrlnout_init((ioport8_t *) gxemul_kbd);
}
void gxemul_input_init(void)
{
#ifdef CONFIG_ARM_KBD
/*
* Initialize the GXemul keyboard port. Then initialize the serial line
* module and connect it to the GXemul keyboard.
*/
dsrlnin_instance_t *dsrlnin_instance
= dsrlnin_init((dsrlnin_t *) gxemul_kbd, GXEMUL_KBD_IRQ);
if (dsrlnin_instance) {
srln_instance_t *srln_instance = srln_init();
if (srln_instance) {
indev_t *sink = stdin_wire();
indev_t *srln = srln_wire(srln_instance, sink);
dsrlnin_wire(dsrlnin_instance, srln);
}
}
/*
* This is the necessary evil until the userspace driver is entirely
* self-sufficient.
*/
sysinfo_set_item_val("kbd", NULL, true);
sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ);
sysinfo_set_item_val("kbd.address.virtual", NULL, (unative_t) gxemul_kbd);
#endif
}
/** Starts gxemul Real Time Clock device, which asserts regular interrupts.
*
* @param frequency Interrupts frequency (0 disables RTC).
*/
static void gxemul_timer_start(uint32_t frequency)
{
*((uint32_t *) (gxemul_rtc + GXEMUL_RTC_FREQ_OFFSET))
= frequency;
}
static irq_ownership_t gxemul_timer_claim(irq_t *irq)
{
return IRQ_ACCEPT;
}
/** Timer interrupt handler.
*
* @param irq Interrupt information.
* @param arg Not used.
*/
static void gxemul_timer_irq_handler(irq_t *irq)
{
/*
* We are holding a lock which prevents preemption.
* Release the lock, call clock() and reacquire the lock again.
*/
spinlock_unlock(&irq->lock);
clock();
spinlock_lock(&irq->lock);
/* acknowledge tick */
*((uint32_t *) (gxemul_rtc + GXEMUL_RTC_ACK_OFFSET))
= 0;
}
/** Initializes and registers timer interrupt handler. */
static void gxemul_timer_irq_init(void)
{
irq_initialize(&gxemul_timer_irq);
gxemul_timer_irq.devno = device_assign_devno();
gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ;
gxemul_timer_irq.claim = gxemul_timer_claim;
gxemul_timer_irq.handler = gxemul_timer_irq_handler;
irq_register(&gxemul_timer_irq);
}
/** Starts timer.
*
* Initiates regular timer interrupts after initializing
* corresponding interrupt handler.
*/
void gxemul_timer_irq_start(void)
{
gxemul_timer_irq_init();
gxemul_timer_start(GXEMUL_TIMER_FREQ);
}
/** Returns the size of emulated memory.
*
* @return Size in bytes.
*/
uintptr_t gxemul_get_memory_size(void)
{
return *((uintptr_t *) (GXEMUL_MP_ADDRESS + GXEMUL_MP_MEMSIZE_OFFSET));
}
/** Returns the mask of active interrupts. */
static inline uint32_t gxemul_irqc_get_sources(void)
{
return *((uint32_t *) gxemul_irqc);
}
/** Interrupt Exception handler.
*
* Determines the sources of interrupt and calls their handlers.
*/
void gxemul_irq_exception(int exc_no, istate_t *istate)
{
uint32_t sources = gxemul_irqc_get_sources();
unsigned int i;
for (i = 0; i < GXEMUL_IRQC_MAX_IRQ; i++) {
if (sources & (1 << i)) {
irq_t *irq = irq_dispatch_and_lock(i);
if (irq) {
/* The IRQ handler was found. */
irq->handler(irq);
spinlock_unlock(&irq->lock);
} else {
/* Spurious interrupt.*/
printf("cpu%d: spurious interrupt (inum=%d)\n",
CPU->id, i);
}
}
}
}
void gxemul_cpu_halt(void)
{
*((char *) (gxemul_kbd + GXEMUL_HALT_OFFSET)) = 0;
}
void gxemul_frame_init(void)
{
}
uintptr_t gxemul_get_fb_address()
{
return ((uintptr_t)GXEMUL_FB_ADDRESS);
}
/** @}
*/
Property changes:
Added: svn:mergeinfo

/branches/tracing/kernel/arch/arm32/src/mach/integratorcp/integratorcp.c
0,0 → 1,360
/*
* Copyright (c) 2009 Vineeth Pillai
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup arm32integratorcp
* @{
*/
/** @file
* @brief ICP drivers.
*/
#include <interrupt.h>
#include <ipc/irq.h>
#include <console/chardev.h>
#include <genarch/drivers/pl050/pl050.h>
#include <genarch/kbrd/kbrd.h>
#include <console/console.h>
#include <sysinfo/sysinfo.h>
#include <print.h>
#include <ddi/device.h>
#include <mm/page.h>
#include <mm/frame.h>
#include <arch/mm/frame.h>
#include <arch/mach/integratorcp/integratorcp.h>
#include <genarch/fb/fb.h>
#include <genarch/fb/visuals.h>
#include <ddi/ddi.h>
#include <print.h>
#define SDRAM_SIZE (sdram[((*(uint32_t *)(ICP_CMCR+ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2)])
static parea_t fb_parea;
static icp_hw_map_t icp_hw_map;
static irq_t icp_timer_irq;
struct arm_machine_ops machine_ops = {
MACHINE_GENFUNC,
MACHINE_GENFUNC,
icp_init,
icp_timer_irq_start,
icp_cpu_halt,
icp_get_memory_size,
icp_fb_init,
icp_irq_exception,
icp_get_fb_address,
icp_frame_init,
icp_output_init,
icp_input_init
};
static bool hw_map_init_called = false;
static bool vga_init = false;
uint32_t sdram[8] = {
16777216, /* 16mb */
33554432, /* 32mb */
67108864, /* 64mb */
134217728, /* 128mb */
268435456, /* 256mb */
0, /* Reserverd */
0, /* Reserverd */
0 /* Reserverd */
};
void icp_vga_init(void);
/** Initializes the vga
*
*/
void icp_vga_init(void)
{
*(uint32_t*)((char *)(icp_hw_map.cmcr)+0x14) = 0xA05F0000;
*(uint32_t*)((char *)(icp_hw_map.cmcr)+0x1C) = 0x12C11000;
*(uint32_t*)icp_hw_map.vga = 0x3F1F3F9C;
*(uint32_t*)((char *)(icp_hw_map.vga) + 0x4) = 0x080B61DF;
*(uint32_t*)((char *)(icp_hw_map.vga) + 0x8) = 0x067F3800;
*(uint32_t*)((char *)(icp_hw_map.vga) + 0x10) = ICP_FB;
*(uint32_t *)((char *)(icp_hw_map.vga) + 0x1C) = 0x182B;
*(uint32_t*)((char *)(icp_hw_map.cmcr)+0xC) = 0x33805000;
}
/** Returns the mask of active interrupts. */
static inline uint32_t icp_irqc_get_sources(void)
{
return *((uint32_t *) icp_hw_map.irqc);
}
/** Masks interrupt.
*
* @param irq interrupt number
*/
static inline void icp_irqc_mask(uint32_t irq)
{
*((uint32_t *) icp_hw_map.irqc_mask) = (1 << irq);
}
/** Unmasks interrupt.
*
* @param irq interrupt number
*/
static inline void icp_irqc_unmask(uint32_t irq)
{
*((uint32_t *) icp_hw_map.irqc_unmask) |= (1 << irq);
}
/** Initializes the icp frame buffer */
void icp_fb_init(void)
{
fb_properties_t prop = {
.addr = 0,
.offset = 0,
.x = 640,
.y = 480,
.scan = 2560,
.visual = VISUAL_BGR_0_8_8_8,
};
prop.addr = icp_get_fb_address();
fb_init(&prop);
fb_parea.pbase = ICP_FB;
fb_parea.frames = 300;
ddi_parea_register(&fb_parea);
}
/** Initializes icp_hw_map. */
void icp_init(void)
{
icp_hw_map.uart = hw_map(ICP_UART, PAGE_SIZE);
icp_hw_map.kbd_ctrl = hw_map(ICP_KBD, PAGE_SIZE);
icp_hw_map.kbd_stat = icp_hw_map.kbd_ctrl + ICP_KBD_STAT;
icp_hw_map.kbd_data = icp_hw_map.kbd_ctrl + ICP_KBD_DATA;
icp_hw_map.kbd_intstat = icp_hw_map.kbd_ctrl + ICP_KBD_INTR_STAT;
icp_hw_map.rtc = hw_map(ICP_RTC, PAGE_SIZE);
icp_hw_map.rtc1_load = icp_hw_map.rtc + ICP_RTC1_LOAD_OFFSET;
icp_hw_map.rtc1_read = icp_hw_map.rtc + ICP_RTC1_READ_OFFSET;
icp_hw_map.rtc1_ctl = icp_hw_map.rtc + ICP_RTC1_CTL_OFFSET;
icp_hw_map.rtc1_intrclr = icp_hw_map.rtc + ICP_RTC1_INTRCLR_OFFSET;
icp_hw_map.rtc1_bgload = icp_hw_map.rtc + ICP_RTC1_BGLOAD_OFFSET;
icp_hw_map.rtc1_intrstat = icp_hw_map.rtc + ICP_RTC1_INTRSTAT_OFFSET;
icp_hw_map.irqc = hw_map(ICP_IRQC, PAGE_SIZE);
icp_hw_map.irqc_mask = icp_hw_map.irqc + ICP_IRQC_MASK_OFFSET;
icp_hw_map.irqc_unmask = icp_hw_map.irqc + ICP_IRQC_UNMASK_OFFSET;
icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE);
icp_hw_map.sdramcr = icp_hw_map.cmcr + ICP_SDRAMCR_OFFSET;
icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE);
hw_map_init_called = true;
}
/** Acquire console back for kernel. */
void icp_grab_console(void)
{
}
/** Return console to userspace. */
void icp_release_console(void)
{
}
/** Starts icp Real Time Clock device, which asserts regular interrupts.
*
* @param frequency Interrupts frequency (0 disables RTC).
*/
static void icp_timer_start(uint32_t frequency)
{
icp_irqc_mask(ICP_TIMER_IRQ);
*((uint32_t*) icp_hw_map.rtc1_load) = frequency;
*((uint32_t*) icp_hw_map.rtc1_bgload) = frequency;
*((uint32_t*) icp_hw_map.rtc1_ctl) = ICP_RTC_CTL_VALUE;
icp_irqc_unmask(ICP_TIMER_IRQ);
}
static irq_ownership_t icp_timer_claim(irq_t *irq)
{
if (icp_hw_map.rtc1_intrstat) {
*((uint32_t*) icp_hw_map.rtc1_intrclr) = 1;
return IRQ_ACCEPT;
} else
return IRQ_DECLINE;
}
/** Timer interrupt handler.
*
* @param irq Interrupt information.
* @param arg Not used.
*/
static void icp_timer_irq_handler(irq_t *irq)
{
/*
* We are holding a lock which prevents preemption.
* Release the lock, call clock() and reacquire the lock again.
*/
spinlock_unlock(&irq->lock);
clock();
spinlock_lock(&irq->lock);
}
/** Initializes and registers timer interrupt handler. */
static void icp_timer_irq_init(void)
{
irq_initialize(&icp_timer_irq);
icp_timer_irq.devno = device_assign_devno();
icp_timer_irq.inr = ICP_TIMER_IRQ;
icp_timer_irq.claim = icp_timer_claim;
icp_timer_irq.handler = icp_timer_irq_handler;
irq_register(&icp_timer_irq);
}
/** Starts timer.
*
* Initiates regular timer interrupts after initializing
* corresponding interrupt handler.
*/
void icp_timer_irq_start(void)
{
icp_timer_irq_init();
icp_timer_start(ICP_TIMER_FREQ);
}
/** Returns the size of emulated memory.
*
* @return Size in bytes.
*/
size_t icp_get_memory_size(void)
{
if (hw_map_init_called) {
return (sdram[((*(uint32_t *)icp_hw_map.sdramcr & ICP_SDRAM_MASK) >> 2)]);
} else {
return SDRAM_SIZE;
}
}
/** Stops icp. */
void icp_cpu_halt(void)
{
while (1);
}
/** interrupt exception handler.
*
* Determines sources of the interrupt from interrupt controller and
* calls high-level handlers for them.
*
* @param exc_no Interrupt exception number.
* @param istate Saved processor state.
*/
void icp_irq_exception(int exc_no, istate_t *istate)
{
uint32_t sources = icp_irqc_get_sources();
int i;
for (i = 0; i < ICP_IRQC_MAX_IRQ; i++) {
if (sources & (1 << i)) {
irq_t *irq = irq_dispatch_and_lock(i);
if (irq) {
/* The IRQ handler was found. */
irq->handler(irq);
spinlock_unlock(&irq->lock);
} else {
/* Spurious interrupt.*/
printf("cpu%d: spurious interrupt (inum=%d)\n",
CPU->id, i);
}
}
}
}
/** Returns address of framebuffer device.
*
* @return Address of framebuffer device.
*/
uintptr_t icp_get_fb_address(void)
{
if (!vga_init) {
icp_vga_init();
vga_init = true;
}
return (uintptr_t) ICP_FB;
}
/*
* Integrator specific frame initialization
*/
void
icp_frame_init(void)
{
frame_mark_unavailable(ICP_FB_FRAME, ICP_FB_NUM_FRAME);
frame_mark_unavailable(0, 256);
}
void icp_output_init(void)
{
}
void icp_input_init(void)
{
pl050_t *pl050 = malloc(sizeof(pl050_t), FRAME_ATOMIC);
pl050->status = (ioport8_t *)icp_hw_map.kbd_stat;
pl050->data = (ioport8_t *)icp_hw_map.kbd_data;
pl050->ctrl = (ioport8_t *)icp_hw_map.kbd_ctrl;
pl050_instance_t *pl050_instance = pl050_init(pl050, ICP_KBD_IRQ);
if (pl050_instance) {
kbrd_instance_t *kbrd_instance = kbrd_init();
if (kbrd_instance) {
icp_irqc_mask(ICP_KBD_IRQ);
indev_t *sink = stdin_wire();
indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
pl050_wire(pl050_instance, kbrd);
icp_irqc_unmask(ICP_KBD_IRQ);
}
}
/*
* This is the necessary evil until the userspace driver is entirely
* self-sufficient.
*/
sysinfo_set_item_val("kbd", NULL, true);
sysinfo_set_item_val("kbd.inr", NULL, ICP_KBD_IRQ);
sysinfo_set_item_val("kbd.address.status", NULL,
(uintptr_t) icp_hw_map.kbd_stat);
sysinfo_set_item_val("kbd.address.data", NULL,
(uintptr_t) icp_hw_map.kbd_data);
}
/** @}
*/

/branches/tracing/kernel/arch/arm32/src/mm/tlb.c
80,7 → 80,7
* @param page Address of the first page whose entry is to be invalidated.
* @param cnt Number of entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, count_t cnt)
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt)
{
unsigned int i;

/branches/tracing/kernel/arch/arm32/src/mm/frame.c
35,9 → 35,16
#include <mm/frame.h>
#include <arch/mm/frame.h>
#include <arch/drivers/gxemul.h>
#include <config.h>
#ifdef MACHINE_testarm
#include <arch/mach/testarm/testarm.h>
#endif
#ifdef MACHINE_integratorcp
#include <arch/mach/integratorcp/integratorcp.h>
#endif
/** Address of the last frame in the memory. */
uintptr_t last_frame = 0;
44,7 → 51,7
/** Creates memory zones. */
void frame_arch_init(void)
{
last_frame = *((uintptr_t *) (GXEMUL_MP_ADDRESS + GXEMUL_MP_MEMSIZE_OFFSET));
last_frame = machine_get_memory_size();
/* All memory as one zone */
zone_create(0, ADDR2PFN(last_frame),
53,6 → 60,8
/* blacklist boot page table */
frame_mark_unavailable(BOOT_PAGE_TABLE_START_FRAME,
BOOT_PAGE_TABLE_SIZE_IN_FRAMES);
machine_frame_init();
}
/** Frees the boot page table. */

/branches/tracing/kernel/arch/arm32/src/interrupt.c
35,16 → 35,21
#include <arch/asm.h>
#include <arch/regutils.h>
#include <arch/drivers/gxemul.h>
#include <ddi/irq.h>
#include <ddi/device.h>
#include <interrupt.h>
#ifdef MACHINE_testarm
#include <arch/mach/testarm/testarm.h>
#endif
#ifdef MACHINE_integratorcp
#include <arch/mach/integratorcp/integratorcp.h>
#endif
/** Initial size of a table holding interrupt handlers. */
#define IRQ_COUNT 8
static irq_t gxemul_timer_irq;
/** Disable interrupts.
*
* @return Old interrupt priority level.
52,7 → 57,7
ipl_t interrupts_disable(void)
{
ipl_t ipl = current_status_reg_read();
current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl);
return ipl;
65,7 → 70,7
ipl_t interrupts_enable(void)
{
ipl_t ipl = current_status_reg_read();
current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
return ipl;
91,41 → 96,6
return current_status_reg_read();
}
/** Starts gxemul Real Time Clock device, which asserts regular interrupts.
*
* @param frequency Interrupts frequency (0 disables RTC).
*/
static void gxemul_timer_start(uint32_t frequency)
{
*((uint32_t *) (gxemul_rtc + GXEMUL_RTC_FREQ_OFFSET))
= frequency;
}
static irq_ownership_t gxemul_timer_claim(irq_t *irq)
{
return IRQ_ACCEPT;
}
/** Timer interrupt handler.
*
* @param irq Interrupt information.
* @param arg Not used.
*/
static void gxemul_timer_irq_handler(irq_t *irq)
{
/*
* We are holding a lock which prevents preemption.
* Release the lock, call clock() and reacquire the lock again.
*/
spinlock_unlock(&irq->lock);
clock();
spinlock_lock(&irq->lock);
/* acknowledge tick */
*((uint32_t *) (gxemul_rtc + GXEMUL_RTC_ACK_OFFSET))
= 0;
}
/** Initialize basic tables for exception dispatching
* and starts the timer.
*/
132,16 → 102,7
void interrupt_init(void)
{
irq_init(IRQ_COUNT, IRQ_COUNT);
irq_initialize(&gxemul_timer_irq);
gxemul_timer_irq.devno = device_assign_devno();
gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ;
gxemul_timer_irq.claim = gxemul_timer_claim;
gxemul_timer_irq.handler = gxemul_timer_irq_handler;
irq_register(&gxemul_timer_irq);
gxemul_timer_start(GXEMUL_TIMER_FREQ);
machine_timer_irq_start();
}
/** @}

/branches/tracing/kernel/arch/arm32/src/exc_handler.S
0,0 → 1,199
#
# Copyright (c) 2009 Vineeth Pillai
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global irq_exception_entry
.global fiq_exception_entry
.global data_abort_exception_entry
.global prefetch_abort_exception_entry
.global undef_instr_exception_entry
.global swi_exception_entry
.global reset_exception_entry
# Switches to kernel stack and saves all registers there.
#
# The stack frame created by the function looks like:
#
# |_________________|
# | |
# | SPSR |
# | |
# |_________________|
# | Stack Pointer |
# | of |
# | Previous Mode |
# |_________________|
# | Return address |
# | of |
# | Previous Mode |
# |_________________|
# | R0 - R12 |
# | of |
# | Previous Mode |
# |_________________|
# | Return address |
# | from |
# |Exception Handler|
# |_________________|
# | |
#
#
.macro SAVE_REGS_TO_STACK
stmfd r13!, {r0-r3}
mov r3, sp
add sp, sp, #16
mrs r1, cpsr
bic r1, r1, #0x1f
mrs r2, spsr
and r0, r2, #0x1f
cmp r0, #0x10
bne 1f
# prev mode was usermode
mov r0, lr
# Switch to supervisor mode
orr r1, r1, #0x13
msr cpsr_c, r1
# Load sp with [supervisor_sp]
ldr r13, =supervisor_sp
ldr r13, [r13]
# Populate the stack frame
msr spsr, r2
mov lr, r0
stmfd r13!, {lr}
stmfd r13!, {r4-r12}
ldmfd r3!, {r4-r7}
stmfd r13!, {r4-r7}
stmfd r13!, {r13, lr}^
stmfd r13!, {r2}
b 2f
# mode was not usermode
1:
# Switch to previous mode which is undoubtedly the supervisor mode
orr r1, r1, r0
mov r0, lr
msr cpsr_c, r1
# Populate the stack frame
mov r1, sp
stmfd r13!, {r0}
stmfd r13!, {r4-r12}
# Store r0-r3 in r4-r7 and then push it on to stack
ldmfd r3!, {r4-r7}
stmfd r13!, {r4-r7}
# Push return address and stack pointer on to stack
stmfd r13!, {lr}
stmfd r13!, {r1}
mov lr, r0
msr spsr, r2
stmfd r13!, {r2}
2:
.endm
.macro LOAD_REGS_FROM_STACK
ldmfd r13!, {r0}
msr spsr, r0
and r0, r0, #0x1f
cmp r0, #0x10
bne 1f
# return to user mode
ldmfd r13!, {r13, lr}^
b 2f
# return to non-user mode
1:
ldmfd r13!, {r1, lr}
2:
ldmfd r13!, {r0-r12, pc}^
.endm
reset_exception_entry:
SAVE_REGS_TO_STACK
mov r0, #0
mov r1, r13
bl exc_dispatch
LOAD_REGS_FROM_STACK
irq_exception_entry:
sub lr, lr, #4
SAVE_REGS_TO_STACK
mov r0, #5
mov r1, r13
bl exc_dispatch
LOAD_REGS_FROM_STACK
fiq_exception_entry:
sub lr, lr, #4
SAVE_REGS_TO_STACK
mov r0, #6
mov r1, r13
bl exc_dispatch
LOAD_REGS_FROM_STACK
undef_instr_exception_entry:
SAVE_REGS_TO_STACK
mov r0, #1
mov r1, r13
bl exc_dispatch
LOAD_REGS_FROM_STACK
prefetch_abort_exception_entry:
sub lr, lr, #4
SAVE_REGS_TO_STACK
mov r0, #3
mov r1, r13
bl exc_dispatch
LOAD_REGS_FROM_STACK
data_abort_exception_entry:
sub lr, lr, #8
SAVE_REGS_TO_STACK
mov r0, #4
mov r1, r13
bl exc_dispatch
LOAD_REGS_FROM_STACK
swi_exception_entry:
ldr r13, =exc_stack
SAVE_REGS_TO_STACK
mov r0, #2
mov r1, r13
bl exc_dispatch
LOAD_REGS_FROM_STACK

/branches/tracing/kernel/arch/arm32/src/drivers/gxemul.c
File deleted

/branches/tracing/kernel/arch/ppc32/include/byteorder.h
File deleted

/branches/tracing/kernel/arch/ppc32/include/types.h
46,8 → 46,6
typedef unsigned long long uint64_t;
typedef uint32_t size_t;
typedef uint32_t count_t;
typedef uint32_t index_t;
typedef uint32_t uintptr_t;
typedef uint32_t pfn_t;
60,11 → 58,9
typedef struct {
} fncptr_t;
/**< Formats for uintptr_t, size_t, count_t and index_t */
/**< Formats for uintptr_t, size_t */
#define PRIp "x"
#define PRIs "u"
#define PRIc "u"
#define PRIi "u"
/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
#define PRId8 "d"

/branches/tracing/kernel/arch/ppc32/include/mm/page.h
102,21 → 102,21
/* Get PTE flags accessors for each level. */
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
get_pt_flags((pte_t *) (ptl0), (index_t) (i))
get_pt_flags((pte_t *) (ptl0), (size_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
get_pt_flags((pte_t *) (ptl3), (index_t) (i))
get_pt_flags((pte_t *) (ptl3), (size_t) (i))
/* Set PTE flags accessors for each level. */
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
/* Macros for querying the last-level PTEs. */
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
130,7 → 130,7
#include <mm/mm.h>
#include <arch/interrupt.h>
static inline int get_pt_flags(pte_t *pt, index_t i)
static inline int get_pt_flags(pte_t *pt, size_t i)
{
pte_t *p = &pt[i];
143,7 → 143,7
(p->global << PAGE_GLOBAL_SHIFT));
}
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
{
pte_t *p = &pt[i];

/branches/tracing/kernel/arch/ppc32/Makefile.inc
39,7 → 39,8
AFLAGS += -a32
LFLAGS += -no-check-sections -N
DEFS += -D__32_BITS__
BITS = 32
ENDIANESS = BE
ARCH_SOURCES = \
arch/$(KARCH)/src/context.S \

/branches/tracing/kernel/arch/ppc32/src/ppc32.c
36,6 → 36,7
#include <arch.h>
#include <arch/boot/boot.h>
#include <genarch/drivers/via-cuda/cuda.h>
#include <genarch/kbrd/kbrd.h>
#include <arch/interrupt.h>
#include <genarch/fb/fb.h>
#include <genarch/fb/visuals.h>
91,10 → 92,10
visual = VISUAL_INDIRECT_8;
break;
case 16:
visual = VISUAL_RGB_5_5_5;
visual = VISUAL_RGB_5_5_5_BE;
break;
case 24:
visual = VISUAL_RGB_8_8_8;
visual = VISUAL_BGR_8_8_8;
break;
case 32:
visual = VISUAL_RGB_0_8_8_8;
117,31 → 118,6
/* Initialize IRQ routing */
irq_init(IRQ_COUNT, IRQ_COUNT);
if (bootinfo.macio.addr) {
/* Initialize PIC */
cir_t cir;
void *cir_arg;
pic_init(bootinfo.macio.addr, PAGE_SIZE, &cir, &cir_arg);
#ifdef CONFIG_VIA_CUDA
uintptr_t pa = bootinfo.macio.addr + 0x16000;
uintptr_t aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE);
size_t offset = pa - aligned_addr;
size_t size = 2 * PAGE_SIZE;
cuda_t *cuda = (cuda_t *)
(hw_map(aligned_addr, offset + size) + offset);
/* Initialize I/O controller */
cuda_instance_t *cuda_instance =
cuda_init(cuda, IRQ_CUDA, cir, cir_arg);
if (cuda_instance) {
indev_t *sink = stdin_wire();
cuda_wire(cuda_instance, sink);
}
#endif
}
/* Merge all zones to 1 big zone */
zone_merge_all();
}
157,6 → 133,35
void arch_post_smp_init(void)
{
if (bootinfo.macio.addr) {
/* Initialize PIC */
cir_t cir;
void *cir_arg;
pic_init(bootinfo.macio.addr, PAGE_SIZE, &cir, &cir_arg);
#ifdef CONFIG_MAC_KBD
uintptr_t pa = bootinfo.macio.addr + 0x16000;
uintptr_t aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE);
size_t offset = pa - aligned_addr;
size_t size = 2 * PAGE_SIZE;
cuda_t *cuda = (cuda_t *)
(hw_map(aligned_addr, offset + size) + offset);
/* Initialize I/O controller */
cuda_instance_t *cuda_instance =
cuda_init(cuda, IRQ_CUDA, cir, cir_arg);
if (cuda_instance) {
kbrd_instance_t *kbrd_instance = kbrd_init();
if (kbrd_instance) {
indev_t *sink = stdin_wire();
indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
cuda_wire(cuda_instance, kbrd);
pic_enable_interrupt(IRQ_CUDA);
}
}
#endif
}
}
void calibrate_delay_loop(void)

/branches/tracing/kernel/arch/ppc32/src/mm/tlb.c
549,7 → 549,7
}
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
{
// TODO
tlb_invalidate_all();

/branches/tracing/kernel/arch/ppc32/src/mm/frame.c
57,7 → 57,7
void frame_arch_init(void)
{
pfn_t minconf = 2;
count_t i;
size_t i;
pfn_t start, conf;
size_t size;

/branches/tracing/kernel/arch/amd64/include/byteorder.h
File deleted

/branches/tracing/kernel/arch/amd64/include/types.h
46,8 → 46,6
typedef unsigned long long uint64_t;
typedef uint64_t size_t;
typedef uint64_t count_t;
typedef uint64_t index_t;
typedef uint64_t uintptr_t;
typedef uint64_t pfn_t;
60,11 → 58,9
typedef struct {
} fncptr_t;
/**< Formats for uintptr_t, size_t, count_t and index_t */
/**< Formats for uintptr_t, size_t */
#define PRIp "llx"
#define PRIs "llu"
#define PRIc "llu"
#define PRIi "llu"
/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
#define PRId8 "d"

/branches/tracing/kernel/arch/amd64/include/atomic.h
115,9 → 115,7
preemption_disable();
asm volatile (
"0:\n"
#ifdef CONFIG_HT
"pause\n"
#endif
"mov %[count], %[tmp]\n"
"testq %[tmp], %[tmp]\n"
"jnz 0b\n" /* lightweight looping on locked spinlock */

/branches/tracing/kernel/arch/amd64/include/proc/task.h
40,7 → 40,7
typedef struct {
/** I/O Permission bitmap Generation counter. */
count_t iomapver;
size_t iomapver;
/** I/O Permission bitmap. */
bitmap_t iomap;
} task_arch_t;

/branches/tracing/kernel/arch/amd64/include/mm/page.h
112,33 → 112,33
#define SET_PTL0_ADDRESS_ARCH(ptl0) \
(write_cr3((uintptr_t) (ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
set_pt_addr((pte_t *) (ptl0), (index_t) (i), a)
set_pt_addr((pte_t *) (ptl0), (size_t) (i), a)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \
set_pt_addr((pte_t *) (ptl1), (index_t) (i), a)
set_pt_addr((pte_t *) (ptl1), (size_t) (i), a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \
set_pt_addr((pte_t *) (ptl2), (index_t) (i), a)
set_pt_addr((pte_t *) (ptl2), (size_t) (i), a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
set_pt_addr((pte_t *) (ptl3), (index_t) (i), a)
set_pt_addr((pte_t *) (ptl3), (size_t) (i), a)
/* Get PTE flags accessors for each level. */
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
get_pt_flags((pte_t *) (ptl0), (index_t) (i))
get_pt_flags((pte_t *) (ptl0), (size_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
get_pt_flags((pte_t *) (ptl1), (index_t) (i))
get_pt_flags((pte_t *) (ptl1), (size_t) (i))
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
get_pt_flags((pte_t *) (ptl2), (index_t) (i))
get_pt_flags((pte_t *) (ptl2), (size_t) (i))
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
get_pt_flags((pte_t *) (ptl3), (index_t) (i))
get_pt_flags((pte_t *) (ptl3), (size_t) (i))
/* Set PTE flags accessors for each level. */
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \
set_pt_flags((pte_t *) (ptl1), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl1), (size_t) (i), (x))
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \
set_pt_flags((pte_t *) (ptl2), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl2), (size_t) (i), (x))
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
/* Macros for querying the last-level PTE entries. */
#define PTE_VALID_ARCH(p) \
176,7 → 176,7
*/
#define PFERR_CODE_ID (1 << 4)
static inline int get_pt_flags(pte_t *pt, index_t i)
static inline int get_pt_flags(pte_t *pt, size_t i)
{
pte_t *p = &pt[i];
189,7 → 189,7
p->global << PAGE_GLOBAL_SHIFT);
}
static inline void set_pt_addr(pte_t *pt, index_t i, uintptr_t a)
static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
{
pte_t *p = &pt[i];
197,7 → 197,7
p->addr_32_51 = a >> 32;
}
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
{
pte_t *p = &pt[i];

/branches/tracing/kernel/arch/amd64/include/cpu.h
64,7 → 64,7
int stepping;
tss_t *tss;
count_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
size_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
} cpu_arch_t;
struct star_msr {

/branches/tracing/kernel/arch/amd64/Makefile.inc
41,7 → 41,8
ICC_CFLAGS += $(CMN1)
SUNCC_CFLAGS += -m64 -xmodel=kernel
DEFS += -D__64_BITS__
BITS = 64
ENDIANESS = LE
## Accepted CPUs
#

/branches/tracing/kernel/arch/amd64/src/ddi/ddi.c
56,7 → 56,7
*/
int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
{
count_t bits;
size_t bits;
bits = ioaddr + size;
if (bits > IO_PORTS)
98,7 → 98,7
/*
* Enable the range and we are done.
*/
bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size);
bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size);
/*
* Increment I/O Permission bitmap generation counter.
117,11 → 117,11
*/
void io_perm_bitmap_install(void)
{
count_t bits;
size_t bits;
ptr_16_64_t cpugdtr;
descriptor_t *gdt_p;
tss_descriptor_t *tss_desc;
count_t ver;
size_t ver;
/* First, copy the I/O Permission Bitmap. */
spinlock_lock(&TASK->lock);

/branches/tracing/kernel/arch/amd64/src/interrupt.c
101,7 → 101,7
static void gp_fault(int n, istate_t *istate)
{
if (TASK) {
count_t ver;
size_t ver;
spinlock_lock(&TASK->lock);
ver = TASK->arch.iomapver;

/branches/tracing/kernel/arch/mips32/include/byteorder.h
File deleted

/branches/tracing/kernel/arch/mips32/include/context_offset.h
86,7 → 86,7
#define EOFFSET_STATUS 0x58
#define EOFFSET_EPC 0x5c
#define EOFFSET_K1 0x60
#define REGISTER_SPACE 100
#define REGISTER_SPACE 104 /* respect stack alignment */
#ifdef __ASM__

/branches/tracing/kernel/arch/mips32/include/types.h
46,8 → 46,6
typedef unsigned long long uint64_t;
typedef uint32_t size_t;
typedef uint32_t count_t;
typedef uint32_t index_t;
typedef uint32_t uintptr_t;
typedef uint32_t pfn_t;
62,8 → 60,6
#define PRIp "x" /**< Format for uintptr_t. */
#define PRIs "u" /**< Format for size_t. */
#define PRIc "u" /**< Format for count_t. */
#define PRIi "u" /**< Format for index_t. */
#define PRId8 "d" /**< Format for int8_t. */
#define PRId16 "d" /**< Format for int16_t. */

/branches/tracing/kernel/arch/mips32/include/elf.h
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup mips32
/** @addtogroup mips32
* @{
*/
/** @file
35,17 → 35,15
#ifndef KERN_mips32_ELF_H_
#define KERN_mips32_ELF_H_
#include <byteorder.h>
#define ELF_MACHINE EM_MIPS
#define ELF_MACHINE EM_MIPS
#ifdef ARCH_IS_BIG_ENDIAN
# define ELF_DATA_ENCODING ELFDATA2MSB
#ifdef __BE__
#define ELF_DATA_ENCODING ELFDATA2MSB
#else
# define ELF_DATA_ENCODING ELFDATA2LSB
#define ELF_DATA_ENCODING ELFDATA2LSB
#endif
#define ELF_CLASS ELFCLASS32
#define ELF_CLASS ELFCLASS32
#endif

/branches/tracing/kernel/arch/mips32/include/atomic.h
88,6 → 88,13
return v;
}
static inline void atomic_lock_arch(atomic_t *val) {
do {
while (val->count)
;
} while (test_and_set(val));
}
#endif
/** @}

/branches/tracing/kernel/arch/mips32/include/arch.h
42,7 → 42,7
#include <typedefs.h>
extern count_t cpu_count;
extern size_t cpu_count;
typedef struct {
uintptr_t addr;

/branches/tracing/kernel/arch/mips32/include/mm/page.h
112,21 → 112,21
/* Get PTE flags accessors for each level. */
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
get_pt_flags((pte_t *) (ptl0), (index_t) (i))
get_pt_flags((pte_t *) (ptl0), (size_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
get_pt_flags((pte_t *) (ptl3), (index_t) (i))
get_pt_flags((pte_t *) (ptl3), (size_t) (i))
/* Set PTE flags accessors for each level. */
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
/* Last-level info macros. */
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
140,7 → 140,7
#include <mm/mm.h>
#include <arch/exception.h>
static inline int get_pt_flags(pte_t *pt, index_t i)
static inline int get_pt_flags(pte_t *pt, size_t i)
{
pte_t *p = &pt[i];
153,7 → 153,7
(p->g << PAGE_GLOBAL_SHIFT));
}
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
{
pte_t *p = &pt[i];

/branches/tracing/kernel/arch/mips32/include/debugger.h
53,7 → 53,7
unative_t instruction; /**< Original instruction */
unative_t nextinstruction; /**< Original instruction following break */
int flags; /**< Flags regarding breakpoint */
count_t counter;
size_t counter;
void (*bkfunc)(void *b, istate_t *istate);
} bpinfo_t;

/branches/tracing/kernel/arch/mips32/Makefile.inc
36,7 → 36,7
GCC_CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3
DEFS += -D__32_BITS__
BITS = 32
## Accepted MACHINEs
#
43,15 → 43,18
ifeq ($(MACHINE),lgxemul)
BFD_NAME = elf32-tradlittlemips
ENDIANESS = LE
endif
ifeq ($(MACHINE),bgxemul)
BFD_NAME = elf32-tradbigmips
TOOLCHAIN_DIR = $(CROSS_PREFIX)/mips
TARGET = mips-linux-gnu
GCC_CFLAGS += -DBIG_ENDIAN
ENDIANESS = BE
GCC_CFLAGS += -D__BE__
endif
ifeq ($(MACHINE),msim)
BFD_NAME = elf32-tradlittlemips
ENDIANESS = LE
GCC_CFLAGS += -mhard-float
endif

/branches/tracing/kernel/arch/mips32/src/mm/tlb.c
560,7 → 560,7
* @param page First page whose TLB entry is to be invalidated.
* @param cnt Number of entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
{
unsigned int i;
ipl_t ipl;

/branches/tracing/kernel/arch/mips32/src/mm/frame.c
62,7 → 62,7
pfn_t count;
} phys_region_t;
static count_t phys_regions_count = 0;
static size_t phys_regions_count = 0;
static phys_region_t phys_regions[MAX_REGIONS];
/** Check whether frame is available
119,7 → 119,7
/* Init tasks */
bool safe = true;
count_t i;
size_t i;
for (i = 0; i < init.cnt; i++)
if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE,
KA2PA(init.tasks[i].addr), init.tasks[i].size)) {
174,7 → 174,7
cp0_entry_lo1_write(0);
cp0_entry_hi_write(0);
count_t i;
size_t i;
for (i = 0; i < TLB_ENTRY_COUNT; i++) {
cp0_index_write(i);
tlbwi();
251,7 → 251,7
printf("Base Size\n");
printf("---------- ----------\n");
count_t i;
size_t i;
for (i = 0; i < phys_regions_count; i++) {
printf("%#010x %10u\n",
PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count));

/branches/tracing/kernel/arch/mips32/src/mips32.c
76,7 → 76,7
/* Stack pointer saved when entering user mode */
uintptr_t supervisor_sp __attribute__ ((section (".text")));
count_t cpu_count = 0;
size_t cpu_count = 0;
/** Performs mips32-specific initialization before main_bsp() is called. */
void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
84,7 → 84,7
/* Setup usermode */
init.cnt = bootinfo->cnt;
count_t i;
size_t i;
for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) {
init.tasks[i].addr = bootinfo->tasks[i].addr;
init.tasks[i].size = bootinfo->tasks[i].size;
141,7 → 141,7
.x = 640,
.y = 480,
.scan = 1920,
.visual = VISUAL_BGR_8_8_8,
.visual = VISUAL_RGB_8_8_8,
};
fb_init(&gxemul_prop);
#else

/branches/tracing/kernel/arch/ia32/include/byteorder.h
File deleted

/branches/tracing/kernel/arch/ia32/include/types.h
46,8 → 46,6
typedef unsigned long long uint64_t;
typedef uint32_t size_t;
typedef uint32_t count_t;
typedef uint32_t index_t;
typedef uint32_t uintptr_t;
typedef uint32_t pfn_t;
62,8 → 60,6
#define PRIp "x" /**< Format for uintptr_t. */
#define PRIs "u" /**< Format for size_t. */
#define PRIc "u" /**< Format for count_t. */
#define PRIi "u" /**< Format for index_t. */
#define PRId8 "d" /**< Format for int8_t. */
#define PRId16 "d" /**< Format for int16_t. */

/branches/tracing/kernel/arch/ia32/include/smp/smp.h
39,10 → 39,10
/** SMP config opertaions interface. */
struct smp_config_operations {
count_t (* cpu_count)(void); /**< Return number of detected processors. */
bool (* cpu_enabled)(index_t i); /**< Check whether the processor of index i is enabled. */
bool (*cpu_bootstrap)(index_t i); /**< Check whether the processor of index i is BSP. */
uint8_t (*cpu_apic_id)(index_t i); /**< Return APIC ID of the processor of index i. */
size_t (* cpu_count)(void); /**< Return number of detected processors. */
bool (* cpu_enabled)(size_t i); /**< Check whether the processor of index i is enabled. */
bool (*cpu_bootstrap)(size_t i); /**< Check whether the processor of index i is BSP. */
uint8_t (*cpu_apic_id)(size_t i); /**< Return APIC ID of the processor of index i. */
int (*irq_to_pin)(unsigned int irq); /**< Return mapping between irq and APIC pin. */
};

/branches/tracing/kernel/arch/ia32/include/atomic.h
114,9 → 114,7
preemption_disable();
asm volatile (
"0:\n"
#ifdef CONFIG_HT
"pause\n" /* Pentium 4's HT love this instruction */
#endif
"mov %[count], %[tmp]\n"
"testl %[tmp], %[tmp]\n"
"jnz 0b\n" /* lightweight looping on locked spinlock */

/branches/tracing/kernel/arch/ia32/include/proc/task.h
40,7 → 40,7
typedef struct {
/** I/O Permission bitmap Generation counter. */
count_t iomapver;
size_t iomapver;
/** I/O Permission bitmap. */
bitmap_t iomap;
} task_arch_t;

/branches/tracing/kernel/arch/ia32/include/mm/page.h
95,21 → 95,21
/* Get PTE flags accessors for each level. */
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
get_pt_flags((pte_t *) (ptl0), (index_t) (i))
get_pt_flags((pte_t *) (ptl0), (size_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
get_pt_flags((pte_t *) (ptl3), (index_t) (i))
get_pt_flags((pte_t *) (ptl3), (size_t) (i))
/* Set PTE flags accessors for each level. */
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
/* Macros for querying the last level entries. */
#define PTE_VALID_ARCH(p) \
145,7 → 145,7
/** When bit on this position is 1, a reserved bit was set in page directory. */
#define PFERR_CODE_RSVD (1 << 3)
static inline int get_pt_flags(pte_t *pt, index_t i)
static inline int get_pt_flags(pte_t *pt, size_t i)
{
pte_t *p = &pt[i];
158,7 → 158,7
p->global << PAGE_GLOBAL_SHIFT);
}
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
{
pte_t *p = &pt[i];

/branches/tracing/kernel/arch/ia32/include/cpu.h
57,7 → 57,7
unsigned int stepping;
tss_t *tss;
count_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
size_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
} cpu_arch_t;
#endif

/branches/tracing/kernel/arch/ia32/Makefile.inc
35,7 → 35,8
TARGET = i686-pc-linux-gnu
TOOLCHAIN_DIR = $(CROSS_PREFIX)/i686
DEFS += -D__32_BITS__
BITS = 32
ENDIANESS = LE
CMN1 = -m32
GCC_CFLAGS += $(CMN1)

/branches/tracing/kernel/arch/ia32/src/smp/mps.c
86,10 → 86,10
/*
* Implementation of IA-32 SMP configuration interface.
*/
static count_t get_cpu_count(void);
static bool is_cpu_enabled(index_t i);
static bool is_bsp(index_t i);
static uint8_t get_cpu_apic_id(index_t i);
static size_t get_cpu_count(void);
static bool is_cpu_enabled(size_t i);
static bool is_bsp(size_t i);
static uint8_t get_cpu_apic_id(size_t i);
static int mps_irq_to_pin(unsigned int irq);
struct smp_config_operations mps_config_operations = {
100,24 → 100,24
.irq_to_pin = mps_irq_to_pin
};
count_t get_cpu_count(void)
size_t get_cpu_count(void)
{
return processor_entry_cnt;
}
bool is_cpu_enabled(index_t i)
bool is_cpu_enabled(size_t i)
{
ASSERT(i < processor_entry_cnt);
return (bool) ((processor_entries[i].cpu_flags & 0x01) == 0x01);
}
bool is_bsp(index_t i)
bool is_bsp(size_t i)
{
ASSERT(i < processor_entry_cnt);
return (bool) ((processor_entries[i].cpu_flags & 0x02) == 0x02);
}
uint8_t get_cpu_apic_id(index_t i)
uint8_t get_cpu_apic_id(size_t i)
{
ASSERT(i < processor_entry_cnt);
return processor_entries[i].l_apic_id;

/branches/tracing/kernel/arch/ia32/src/ddi/ddi.c
57,7 → 57,7
*/
int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
{
count_t bits;
size_t bits;
bits = ioaddr + size;
if (bits > IO_PORTS)
99,7 → 99,7
/*
* Enable the range and we are done.
*/
bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size);
bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size);
/*
* Increment I/O Permission bitmap generation counter.
118,10 → 118,10
*/
void io_perm_bitmap_install(void)
{
count_t bits;
size_t bits;
ptr_16_32_t cpugdtr;
descriptor_t *gdt_p;
count_t ver;
size_t ver;
/* First, copy the I/O Permission Bitmap. */
spinlock_lock(&TASK->lock);

/branches/tracing/kernel/arch/ia32/src/mm/tlb.c
59,7 → 59,7
* @param page Address of the first page whose entry is to be invalidated.
* @param cnt Number of entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, count_t cnt)
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt)
{
unsigned int i;

/branches/tracing/kernel/arch/ia32/src/mm/frame.c
70,7 → 70,7
#endif
pfn_t pfn;
count_t count;
size_t count;
if (e820table[i].type == MEMMAP_MEMORY_AVAILABLE) {
/* To be safe, make available zone possibly smaller */

/branches/tracing/kernel/arch/ia32/src/interrupt.c
101,7 → 101,7
static void gp_fault(int n __attribute__((unused)), istate_t *istate)
{
if (TASK) {
count_t ver;
size_t ver;
spinlock_lock(&TASK->lock);
ver = TASK->arch.iomapver;

/branches/tracing/kernel/arch/ia32/src/atomic.S
42,9 → 42,7
movl 12(%esp),%ebx
0:
#ifdef CONFIG_HT
pause # Pentium 4's with HT love this instruction
#endif
movl (%ebx),%eax
testl %eax,%eax
jnz 0b # lightweight looping while it is locked

/branches/tracing/kernel/arch/ia32/src/drivers/vesa.c
85,15 → 85,15
if ((vesa_red_mask == 5) && (vesa_red_pos == 10)
&& (vesa_green_mask == 5) && (vesa_green_pos == 5)
&& (vesa_blue_mask == 5) && (vesa_blue_pos == 0))
visual = VISUAL_RGB_5_5_5;
visual = VISUAL_RGB_5_5_5_LE;
else
visual = VISUAL_RGB_5_6_5;
visual = VISUAL_RGB_5_6_5_LE;
break;
case 24:
visual = VISUAL_RGB_8_8_8;
visual = VISUAL_BGR_8_8_8;
break;
case 32:
visual = VISUAL_RGB_0_8_8_8;
visual = VISUAL_BGR_8_8_8_0;
break;
default:
panic("Unsupported bits per pixel.");