| /branches/tracing/kernel/arch/mips32/src/mips32.c |
|---|
| 33,17 → 33,20 |
| */ |
| #include <arch.h> |
| #include <arch/boot.h> |
| #include <arch/cp0.h> |
| #include <arch/exception.h> |
| #include <mm/as.h> |
| #include <userspace.h> |
| #include <arch/console.h> |
| #include <memstr.h> |
| #include <proc/thread.h> |
| #include <proc/uarg.h> |
| #include <print.h> |
| #include <console/console.h> |
| #include <syscall/syscall.h> |
| #include <sysinfo/sysinfo.h> |
| #include <arch/interrupt.h> |
| #include <console/chardev.h> |
| #include <arch/barrier.h> |
| 50,51 → 53,39 |
| #include <arch/debugger.h> |
| #include <genarch/fb/fb.h> |
| #include <genarch/fb/visuals.h> |
| #include <genarch/drivers/dsrln/dsrlnin.h> |
| #include <genarch/drivers/dsrln/dsrlnout.h> |
| #include <genarch/srln/srln.h> |
| #include <macros.h> |
| #include <config.h> |
| #include <string.h> |
| #include <arch/drivers/msim.h> |
| #include <ddi/device.h> |
| #include <arch/asm/regname.h> |
| /* Size of the code jumping to the exception handler code |
| * - J+NOP |
| /* Size of the code jumping to the exception handler code |
| * - J+NOP |
| */ |
| #define EXCEPTION_JUMP_SIZE 8 |
| #define EXCEPTION_JUMP_SIZE 8 |
| #define TLB_EXC ((char *) 0x80000000) |
| #define NORM_EXC ((char *) 0x80000180) |
| #define CACHE_EXC ((char *) 0x80000100) |
| #define TLB_EXC ((char *) 0x80000000) |
| #define NORM_EXC ((char *) 0x80000180) |
| #define CACHE_EXC ((char *) 0x80000100) |
| /* Why the linker moves the variable 64K away in assembler |
| * when not in .text section? |
| * when not in .text section ???????? |
| */ |
| uintptr_t supervisor_sp __attribute__ ((section (".text"))); |
| /* Stack pointer saved when entering user mode */ |
| uintptr_t supervisor_sp __attribute__ ((section (".text"))); |
| /* TODO: How do we do it on SMP system???? */ |
| bootinfo_t bootinfo __attribute__ ((section (".text"))); |
| count_t cpu_count = 0; |
| /** Performs mips32-specific initialization before main_bsp() is called. */ |
| void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo) |
| void arch_pre_main(void) |
| { |
| /* Setup usermode */ |
| init.cnt = bootinfo->cnt; |
| init.cnt = bootinfo.cnt; |
| count_t i; |
| for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) { |
| init.tasks[i].addr = bootinfo->tasks[i].addr; |
| init.tasks[i].size = bootinfo->tasks[i].size; |
| str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN, |
| bootinfo->tasks[i].name); |
| } |
| uint32_t i; |
| for (i = 0; i < CPUMAP_MAX_RECORDS; i++) { |
| if ((bootinfo->cpumap & (1 << i)) != 0) |
| cpu_count++; |
| for (i = 0; i < bootinfo.cnt; i++) { |
| init.tasks[i].addr = bootinfo.tasks[i].addr; |
| init.tasks[i].size = bootinfo.tasks[i].size; |
| } |
| } |
| 120,12 → 111,12 |
| */ |
| cp0_status_write(cp0_status_read() & |
| ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit)); |
| /* |
| * Mask all interrupts |
| /* |
| * Mask all interrupts |
| */ |
| cp0_mask_all_int(); |
| debugger_init(); |
| } |
| 132,7 → 123,7 |
| void arch_post_mm_init(void) |
| { |
| interrupt_init(); |
| console_init(device_assign_devno()); |
| #ifdef CONFIG_FB |
| /* GXemul framebuffer */ |
| fb_properties_t gxemul_prop = { |
| 141,14 → 132,11 |
| .x = 640, |
| .y = 480, |
| .scan = 1920, |
| .visual = VISUAL_BGR_8_8_8, |
| .visual = VISUAL_RGB_8_8_8, |
| }; |
| fb_init(&gxemul_prop); |
| #else |
| #ifdef CONFIG_MIPS_PRN |
| dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS); |
| #endif /* CONFIG_MIPS_PRN */ |
| #endif /* CONFIG_FB */ |
| #endif |
| sysinfo_set_item_val("machine." STRING(MACHINE), NULL, 1); |
| } |
| void arch_post_cpu_init(void) |
| 161,37 → 149,8 |
| void arch_post_smp_init(void) |
| { |
| #ifdef CONFIG_MIPS_KBD |
| /* |
| * Initialize the msim/GXemul keyboard port. Then initialize the serial line |
| * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts. |
| */ |
| dsrlnin_instance_t *dsrlnin_instance |
| = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ); |
| if (dsrlnin_instance) { |
| srln_instance_t *srln_instance = srln_init(); |
| if (srln_instance) { |
| indev_t *sink = stdin_wire(); |
| indev_t *srln = srln_wire(srln_instance, sink); |
| dsrlnin_wire(dsrlnin_instance, srln); |
| cp0_unmask_int(MSIM_KBD_IRQ); |
| } |
| } |
| /* |
| * This is the necessary evil until the userspace driver is entirely |
| * self-sufficient. |
| */ |
| sysinfo_set_item_val("kbd", NULL, true); |
| sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ); |
| sysinfo_set_item_val("kbd.address.virtual", NULL, MSIM_KBD_ADDRESS); |
| #endif |
| } |
| void calibrate_delay_loop(void) |
| { |
| } |
| void userspace(uspace_arg_t *kernel_uarg) |
| { |
| /* EXL = 1, UM = 1, IE = 1 */ |
| 202,7 → 161,8 |
| (uintptr_t) kernel_uarg->uspace_uarg, |
| (uintptr_t) kernel_uarg->uspace_entry); |
| while (1); |
| while (1) |
| ; |
| } |
| /** Perform mips32 specific tasks needed before the new task is run. */ |
| 234,36 → 194,10 |
| void arch_reboot(void) |
| { |
| ___halt(); |
| while (1); |
| while (1) |
| ; |
| } |
| /** Construct function pointer |
| * |
| * @param fptr function pointer structure |
| * @param addr function address |
| * @param caller calling function address |
| * |
| * @return address of the function pointer |
| * |
| */ |
| void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller) |
| { |
| return addr; |
| } |
| void arch_grab_console(void) |
| { |
| #ifdef CONFIG_FB |
| fb_redraw(); |
| #endif |
| } |
| /** Return console to userspace |
| * |
| */ |
| void arch_release_console(void) |
| { |
| } |
| /** @} |
| */ |
| /branches/tracing/kernel/arch/mips32/src/mm/tlb.c |
|---|
| 26,7 → 26,7 |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32mm |
| /** @addtogroup mips32mm |
| * @{ |
| */ |
| /** @file |
| 40,12 → 40,12 |
| #include <arch/cp0.h> |
| #include <panic.h> |
| #include <arch.h> |
| #include <synch/mutex.h> |
| #include <symtab.h> |
| #include <synch/spinlock.h> |
| #include <print.h> |
| #include <debug.h> |
| #include <align.h> |
| #include <interrupt.h> |
| #include <symtab.h> |
| static void tlb_refill_fail(istate_t *); |
| static void tlb_invalid_fail(istate_t *); |
| 92,15 → 92,15 |
| uintptr_t badvaddr; |
| pte_t *pte; |
| int pfrc; |
| badvaddr = cp0_badvaddr_read(); |
| mutex_lock(&AS->lock); |
| spinlock_lock(&AS->lock); |
| asid = AS->asid; |
| mutex_unlock(&AS->lock); |
| spinlock_unlock(&AS->lock); |
| page_table_lock(AS, true); |
| pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
| if (!pte) { |
| switch (pfrc) { |
| 115,7 → 115,7 |
| page_table_unlock(AS, true); |
| return; |
| default: |
| panic("Unexpected pfrc (%d).", pfrc); |
| panic("unexpected pfrc (%d)\n", pfrc); |
| } |
| } |
| 199,7 → 199,7 |
| page_table_unlock(AS, true); |
| return; |
| default: |
| panic("Unexpected pfrc (%d).", pfrc); |
| panic("unexpected pfrc (%d)\n", pfrc); |
| } |
| } |
| 282,7 → 282,7 |
| page_table_unlock(AS, true); |
| return; |
| default: |
| panic("Unexpected pfrc (%d).", pfrc); |
| panic("unexpected pfrc (%d)\n", pfrc); |
| } |
| } |
| 320,14 → 320,19 |
| void tlb_refill_fail(istate_t *istate) |
| { |
| char *symbol, *sym2; |
| char *symbol = ""; |
| char *sym2 = ""; |
| symbol = symtab_fmt_name_lookup(istate->epc); |
| sym2 = symtab_fmt_name_lookup(istate->ra); |
| fault_if_from_uspace(istate, "TLB Refill Exception on %p.", |
| char *s = get_symtab_entry(istate->epc); |
| if (s) |
| symbol = s; |
| s = get_symtab_entry(istate->ra); |
| if (s) |
| sym2 = s; |
| fault_if_from_uspace(istate, "TLB Refill Exception on %p", |
| cp0_badvaddr_read()); |
| panic("%x: TLB Refill Exception at %x (%s<-%s).", cp0_badvaddr_read(), |
| panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), |
| istate->epc, symbol, sym2); |
| } |
| 334,25 → 339,27 |
| void tlb_invalid_fail(istate_t *istate) |
| { |
| char *symbol; |
| char *symbol = ""; |
| symbol = symtab_fmt_name_lookup(istate->epc); |
| fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", |
| char *s = get_symtab_entry(istate->epc); |
| if (s) |
| symbol = s; |
| fault_if_from_uspace(istate, "TLB Invalid Exception on %p", |
| cp0_badvaddr_read()); |
| panic("%x: TLB Invalid Exception at %x (%s).", cp0_badvaddr_read(), |
| panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), |
| istate->epc, symbol); |
| } |
| void tlb_modified_fail(istate_t *istate) |
| { |
| char *symbol; |
| char *symbol = ""; |
| symbol = symtab_fmt_name_lookup(istate->epc); |
| fault_if_from_uspace(istate, "TLB Modified Exception on %p.", |
| char *s = get_symtab_entry(istate->epc); |
| if (s) |
| symbol = s; |
| fault_if_from_uspace(istate, "TLB Modified Exception on %p", |
| cp0_badvaddr_read()); |
| panic("%x: TLB Modified Exception at %x (%s).", cp0_badvaddr_read(), |
| panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), |
| istate->epc, symbol); |
| } |
| 426,7 → 433,7 |
| return NULL; |
| break; |
| default: |
| panic("Unexpected rc (%d).", rc); |
| panic("unexpected rc (%d)\n", rc); |
| } |
| } |
| /branches/tracing/kernel/arch/mips32/src/mm/frame.c |
|---|
| 26,7 → 26,7 |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32mm |
| /** @addtogroup mips32mm |
| * @{ |
| */ |
| /** @file |
| 40,22 → 40,22 |
| #include <mm/asid.h> |
| #include <config.h> |
| #include <arch/drivers/msim.h> |
| #include <arch/drivers/serial.h> |
| #include <print.h> |
| #define ZERO_PAGE_MASK TLB_PAGE_MASK_256K |
| #define ZERO_FRAMES 2048 |
| #define ZERO_PAGE_WIDTH 18 /* 256K */ |
| #define ZERO_PAGE_SIZE (1 << ZERO_PAGE_WIDTH) |
| #define ZERO_PAGE_ASID ASID_INVALID |
| #define ZERO_PAGE_TLBI 0 |
| #define ZERO_PAGE_ADDR 0 |
| #define ZERO_PAGE_OFFSET (ZERO_PAGE_SIZE / sizeof(uint32_t) - 1) |
| #define ZERO_PAGE_VALUE (((volatile uint32_t *) ZERO_PAGE_ADDR)[ZERO_PAGE_OFFSET]) |
| #define ZERO_PAGE_MASK TLB_PAGE_MASK_256K |
| #define ZERO_FRAMES 2048 |
| #define ZERO_PAGE_WIDTH 18 /* 256K */ |
| #define ZERO_PAGE_SIZE (1 << ZERO_PAGE_WIDTH) |
| #define ZERO_PAGE_ASID ASID_INVALID |
| #define ZERO_PAGE_TLBI 0 |
| #define ZERO_PAGE_ADDR 0 |
| #define ZERO_PAGE_OFFSET (ZERO_PAGE_SIZE / sizeof(uint32_t) - 1) |
| #define ZERO_PAGE_VALUE (((volatile uint32_t *) ZERO_PAGE_ADDR)[ZERO_PAGE_OFFSET]) |
| #define ZERO_PAGE_VALUE_KSEG1(frame) \ |
| (((volatile uint32_t *) (0xa0000000 + (frame << ZERO_PAGE_WIDTH)))[ZERO_PAGE_OFFSET]) |
| #define ZERO_PAGE_VALUE_KSEG1(frame) (((volatile uint32_t *) (0xa0000000 + (frame << ZERO_PAGE_WIDTH)))[ZERO_PAGE_OFFSET]) |
| #define MAX_REGIONS 32 |
| #define MAX_REGIONS 32 |
| typedef struct { |
| pfn_t start; |
| 65,6 → 65,7 |
| static count_t phys_regions_count = 0; |
| static phys_region_t phys_regions[MAX_REGIONS]; |
| /** Check whether frame is available |
| * |
| * Returns true if given frame is generally available for use. |
| 74,7 → 75,7 |
| */ |
| static bool frame_available(pfn_t frame) |
| { |
| #ifdef MACHINE_msim |
| #if MACHINE == msim |
| /* MSIM device (dprinter) */ |
| if (frame == (KA2PA(MSIM_VIDEORAM) >> ZERO_PAGE_WIDTH)) |
| return false; |
| 83,8 → 84,14 |
| if (frame == (KA2PA(MSIM_KBD_ADDRESS) >> ZERO_PAGE_WIDTH)) |
| return false; |
| #endif |
| #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul) |
| #if MACHINE == simics |
| /* Simics device (serial line) */ |
| if (frame == (KA2PA(SERIAL_ADDRESS) >> ZERO_PAGE_WIDTH)) |
| return false; |
| #endif |
| #if (MACHINE == lgxemul) || (MACHINE == bgxemul) |
| /* gxemul devices */ |
| if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
| 0x10000000, MB2SIZE(256))) |
| 211,7 → 218,7 |
| ZERO_PAGE_VALUE = 0xdeadbeef; |
| if (ZERO_PAGE_VALUE != 0xdeadbeef) |
| avail = false; |
| #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul) |
| #if (MACHINE == lgxemul) || (MACHINE == bgxemul) |
| else { |
| ZERO_PAGE_VALUE_KSEG1(frame) = 0xaabbccdd; |
| if (ZERO_PAGE_VALUE_KSEG1(frame) != 0xaabbccdd) |
| /branches/tracing/kernel/arch/mips32/src/mm/page.c |
|---|
| 26,7 → 26,7 |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32mm |
| /** @addtogroup mips32mm |
| * @{ |
| */ |
| /** @file |
| 35,7 → 35,6 |
| #include <arch/mm/page.h> |
| #include <genarch/mm/page_pt.h> |
| #include <mm/page.h> |
| #include <mm/frame.h> |
| void page_arch_init(void) |
| { |
| /branches/tracing/kernel/arch/mips32/src/exception.c |
|---|
| 41,13 → 41,14 |
| #include <arch.h> |
| #include <debug.h> |
| #include <proc/thread.h> |
| #include <symtab.h> |
| #include <print.h> |
| #include <interrupt.h> |
| #include <func.h> |
| #include <console/kconsole.h> |
| #include <ddi/irq.h> |
| #include <arch/debugger.h> |
| #include <udebug/udebug.h> |
| #include <symtab.h> |
| static char * exctable[] = { |
| "Interrupt", |
| 74,21 → 75,25 |
| static void print_regdump(istate_t *istate) |
| { |
| char *pcsymbol, *rasymbol; |
| char *pcsymbol = ""; |
| char *rasymbol = ""; |
| pcsymbol = symtab_fmt_name_lookup(istate->epc); |
| rasymbol = symtab_fmt_name_lookup(istate->ra); |
| printf("PC: %#x(%s) RA: %#x(%s), SP(%p)\n", istate->epc, pcsymbol, |
| istate->ra, rasymbol, istate->sp); |
| char *s = get_symtab_entry(istate->epc); |
| if (s) |
| pcsymbol = s; |
| s = get_symtab_entry(istate->ra); |
| if (s) |
| rasymbol = s; |
| printf("PC: %#x(%s) RA: %#x(%s), SP(%p)\n", istate->epc, pcsymbol, istate->ra, rasymbol, istate->sp); |
| } |
| static void unhandled_exception(int n, istate_t *istate) |
| { |
| fault_if_from_uspace(istate, "Unhandled exception %s.", exctable[n]); |
| fault_if_from_uspace(istate, "unhandled exception %s", exctable[n]); |
| print_regdump(istate); |
| panic("Unhandled exception %s.", exctable[n]); |
| panic("unhandled exception %s\n", exctable[n]); |
| } |
| static void reserved_instr_exception(int n, istate_t *istate) |
| 137,8 → 142,8 |
| if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id) |
| scheduler_fpu_lazy_request(); |
| else { |
| fault_if_from_uspace(istate, "Unhandled Coprocessor Unusable Exception."); |
| panic("Unhandled Coprocessor Unusable Exception."); |
| fault_if_from_uspace(istate, "unhandled Coprocessor Unusable Exception"); |
| panic("unhandled Coprocessor Unusable Exception\n"); |
| } |
| } |
| #endif |
| 149,7 → 154,7 |
| int i; |
| /* decode interrupt number and process the interrupt */ |
| cause = (cp0_cause_read() >> 8) & 0xff; |
| cause = (cp0_cause_read() >> 8) &0xff; |
| for (i = 0; i < 8; i++) { |
| if (cause & (1 << i)) { |
| 158,7 → 163,7 |
| /* |
| * The IRQ handler was found. |
| */ |
| irq->handler(irq); |
| irq->handler(irq, irq->arg); |
| spinlock_unlock(&irq->lock); |
| } else { |
| /* |
| 165,8 → 170,7 |
| * Spurious interrupt. |
| */ |
| #ifdef CONFIG_DEBUG |
| printf("cpu%u: spurious interrupt (inum=%d)\n", |
| CPU->id, i); |
| printf("cpu%u: spurious interrupt (inum=%d)\n", CPU->id, i); |
| #endif |
| } |
| } |
| 176,7 → 180,7 |
| /** Handle syscall userspace call */ |
| static void syscall_exception(int n, istate_t *istate) |
| { |
| panic("Syscall is handled through shortcut."); |
| panic("Syscall is handled through shortcut"); |
| } |
| void exception_init(void) |
| /branches/tracing/kernel/arch/mips32/src/asm.S |
|---|
| 27,17 → 27,17 |
| # |
| #include <arch/asm/regname.h> |
| .text |
| .macro cp0_read reg |
| mfc0 $2, \reg |
| mfc0 $2,\reg |
| j $31 |
| nop |
| .endm |
| .macro cp0_write reg |
| mtc0 $4, \reg |
| mtc0 $4,\reg |
| j $31 |
| nop |
| .endm |
| 46,11 → 46,6 |
| .set noreorder |
| .set nomacro |
| .global asm_delay_loop |
| asm_delay_loop: |
| j $31 |
| nop |
| .global cpu_halt |
| cpu_halt: |
| j cpu_halt |
| 63,12 → 58,6 |
| nop |
| .global memsetw |
| memsetw: |
| j _memsetw |
| nop |
| .global memcpy |
| .global memcpy_from_uspace |
| .global memcpy_to_uspace |
| 77,238 → 66,235 |
| memcpy: |
| memcpy_from_uspace: |
| memcpy_to_uspace: |
| move $t2, $a0 # save dst |
| addiu $v0, $a1, 3 |
| li $v1, -4 # 0xfffffffffffffffc |
| and $v0, $v0, $v1 |
| beq $a1, $v0, 3f |
| move $t0, $a0 |
| 0: |
| beq $a2, $zero, 2f |
| move $a3, $zero |
| 1: |
| addu $v0, $a1, $a3 |
| lbu $a0, 0($v0) |
| addu $v1, $t0, $a3 |
| addiu $a3, $a3, 1 |
| bne $a3, $a2, 1b |
| sb $a0, 0($v1) |
| 2: |
| jr $ra |
| move $v0, $t2 |
| 3: |
| addiu $v0, $a0, 3 |
| and $v0, $v0, $v1 |
| bne $a0, $v0, 0b |
| srl $t1, $a2, 2 |
| beq $t1, $zero, 5f |
| move $a3, $zero |
| move $a3, $zero |
| move $a0, $zero |
| 4: |
| addu $v0, $a1, $a0 |
| lw $v1, 0($v0) |
| addiu $a3, $a3, 1 |
| addu $v0, $t0, $a0 |
| sw $v1, 0($v0) |
| bne $a3, $t1, 4b |
| addiu $a0, $a0, 4 |
| 5: |
| andi $a2, $a2, 0x3 |
| beq $a2, $zero, 2b |
| nop |
| sll $v0, $a3, 2 |
| addu $t1, $v0, $t0 |
| move $a3, $zero |
| addu $t0, $v0, $a1 |
| 6: |
| addu $v0, $t0, $a3 |
| lbu $a0, 0($v0) |
| addu $v1, $t1, $a3 |
| addiu $a3, $a3, 1 |
| bne $a3, $a2, 6b |
| sb $a0, 0($v1) |
| jr $ra |
| move $v0, $t2 |
| addiu $v0,$a1,3 |
| li $v1,-4 # 0xfffffffffffffffc |
| and $v0,$v0,$v1 |
| beq $a1,$v0,3f |
| move $t0,$a0 |
| move $t2,$a0 # save dst |
| 0: |
| beq $a2,$zero,2f |
| move $a3,$zero |
| 1: |
| addu $v0,$a1,$a3 |
| lbu $a0,0($v0) |
| addu $v1,$t0,$a3 |
| addiu $a3,$a3,1 |
| bne $a3,$a2,1b |
| sb $a0,0($v1) |
| 2: |
| jr $ra |
| move $v0,$t2 |
| 3: |
| addiu $v0,$a0,3 |
| and $v0,$v0,$v1 |
| bne $a0,$v0,0b |
| srl $t1,$a2,2 |
| beq $t1,$zero,5f |
| move $a3,$zero |
| move $a3,$zero |
| move $a0,$zero |
| 4: |
| addu $v0,$a1,$a0 |
| lw $v1,0($v0) |
| addiu $a3,$a3,1 |
| addu $v0,$t0,$a0 |
| sw $v1,0($v0) |
| bne $a3,$t1,4b |
| addiu $a0,$a0,4 |
| 5: |
| andi $a2,$a2,0x3 |
| beq $a2,$zero,2b |
| nop |
| sll $v0,$a3,2 |
| addu $t1,$v0,$t0 |
| move $a3,$zero |
| addu $t0,$v0,$a1 |
| 6: |
| addu $v0,$t0,$a3 |
| lbu $a0,0($v0) |
| addu $v1,$t1,$a3 |
| addiu $a3,$a3,1 |
| bne $a3,$a2,6b |
| sb $a0,0($v1) |
| jr $ra |
| move $v0,$t2 |
| memcpy_from_uspace_failover_address: |
| memcpy_to_uspace_failover_address: |
| jr $ra |
| move $v0, $zero |
| jr $ra |
| move $v0, $zero |
| .macro fpu_gp_save reg ctx |
| mfc1 $t0, $\reg |
| sw $t0, \reg * 4(\ctx) |
| mfc1 $t0,$\reg |
| sw $t0, \reg*4(\ctx) |
| .endm |
| .macro fpu_gp_restore reg ctx |
| lw $t0, \reg * 4(\ctx) |
| mtc1 $t0, $\reg |
| lw $t0, \reg*4(\ctx) |
| mtc1 $t0,$\reg |
| .endm |
| .macro fpu_ct_save reg ctx |
| cfc1 $t0, $1 |
| sw $t0, (\reg + 32) * 4(\ctx) |
| cfc1 $t0,$1 |
| sw $t0, (\reg+32)*4(\ctx) |
| .endm |
| .macro fpu_ct_restore reg ctx |
| lw $t0, (\reg + 32) * 4(\ctx) |
| ctc1 $t0, $\reg |
| lw $t0, (\reg+32)*4(\ctx) |
| ctc1 $t0,$\reg |
| .endm |
| .global fpu_context_save |
| fpu_context_save: |
| #ifdef CONFIG_FPU |
| fpu_gp_save 0, $a0 |
| fpu_gp_save 1, $a0 |
| fpu_gp_save 2, $a0 |
| fpu_gp_save 3, $a0 |
| fpu_gp_save 4, $a0 |
| fpu_gp_save 5, $a0 |
| fpu_gp_save 6, $a0 |
| fpu_gp_save 7, $a0 |
| fpu_gp_save 8, $a0 |
| fpu_gp_save 9, $a0 |
| fpu_gp_save 10, $a0 |
| fpu_gp_save 11, $a0 |
| fpu_gp_save 12, $a0 |
| fpu_gp_save 13, $a0 |
| fpu_gp_save 14, $a0 |
| fpu_gp_save 15, $a0 |
| fpu_gp_save 16, $a0 |
| fpu_gp_save 17, $a0 |
| fpu_gp_save 18, $a0 |
| fpu_gp_save 19, $a0 |
| fpu_gp_save 20, $a0 |
| fpu_gp_save 21, $a0 |
| fpu_gp_save 22, $a0 |
| fpu_gp_save 23, $a0 |
| fpu_gp_save 24, $a0 |
| fpu_gp_save 25, $a0 |
| fpu_gp_save 26, $a0 |
| fpu_gp_save 27, $a0 |
| fpu_gp_save 28, $a0 |
| fpu_gp_save 29, $a0 |
| fpu_gp_save 30, $a0 |
| fpu_gp_save 31, $a0 |
| fpu_ct_save 1, $a0 |
| fpu_ct_save 2, $a0 |
| fpu_ct_save 3, $a0 |
| fpu_ct_save 4, $a0 |
| fpu_ct_save 5, $a0 |
| fpu_ct_save 6, $a0 |
| fpu_ct_save 7, $a0 |
| fpu_ct_save 8, $a0 |
| fpu_ct_save 9, $a0 |
| fpu_ct_save 10, $a0 |
| fpu_ct_save 11, $a0 |
| fpu_ct_save 12, $a0 |
| fpu_ct_save 13, $a0 |
| fpu_ct_save 14, $a0 |
| fpu_ct_save 15, $a0 |
| fpu_ct_save 16, $a0 |
| fpu_ct_save 17, $a0 |
| fpu_ct_save 18, $a0 |
| fpu_ct_save 19, $a0 |
| fpu_ct_save 20, $a0 |
| fpu_ct_save 21, $a0 |
| fpu_ct_save 22, $a0 |
| fpu_ct_save 23, $a0 |
| fpu_ct_save 24, $a0 |
| fpu_ct_save 25, $a0 |
| fpu_ct_save 26, $a0 |
| fpu_ct_save 27, $a0 |
| fpu_ct_save 28, $a0 |
| fpu_ct_save 29, $a0 |
| fpu_ct_save 30, $a0 |
| fpu_ct_save 31, $a0 |
| #endif |
| #ifdef ARCH_HAS_FPU |
| fpu_gp_save 0,$a0 |
| fpu_gp_save 1,$a0 |
| fpu_gp_save 2,$a0 |
| fpu_gp_save 3,$a0 |
| fpu_gp_save 4,$a0 |
| fpu_gp_save 5,$a0 |
| fpu_gp_save 6,$a0 |
| fpu_gp_save 7,$a0 |
| fpu_gp_save 8,$a0 |
| fpu_gp_save 9,$a0 |
| fpu_gp_save 10,$a0 |
| fpu_gp_save 11,$a0 |
| fpu_gp_save 12,$a0 |
| fpu_gp_save 13,$a0 |
| fpu_gp_save 14,$a0 |
| fpu_gp_save 15,$a0 |
| fpu_gp_save 16,$a0 |
| fpu_gp_save 17,$a0 |
| fpu_gp_save 18,$a0 |
| fpu_gp_save 19,$a0 |
| fpu_gp_save 20,$a0 |
| fpu_gp_save 21,$a0 |
| fpu_gp_save 22,$a0 |
| fpu_gp_save 23,$a0 |
| fpu_gp_save 24,$a0 |
| fpu_gp_save 25,$a0 |
| fpu_gp_save 26,$a0 |
| fpu_gp_save 27,$a0 |
| fpu_gp_save 28,$a0 |
| fpu_gp_save 29,$a0 |
| fpu_gp_save 30,$a0 |
| fpu_gp_save 31,$a0 |
| fpu_ct_save 1,$a0 |
| fpu_ct_save 2,$a0 |
| fpu_ct_save 3,$a0 |
| fpu_ct_save 4,$a0 |
| fpu_ct_save 5,$a0 |
| fpu_ct_save 6,$a0 |
| fpu_ct_save 7,$a0 |
| fpu_ct_save 8,$a0 |
| fpu_ct_save 9,$a0 |
| fpu_ct_save 10,$a0 |
| fpu_ct_save 11,$a0 |
| fpu_ct_save 12,$a0 |
| fpu_ct_save 13,$a0 |
| fpu_ct_save 14,$a0 |
| fpu_ct_save 15,$a0 |
| fpu_ct_save 16,$a0 |
| fpu_ct_save 17,$a0 |
| fpu_ct_save 18,$a0 |
| fpu_ct_save 19,$a0 |
| fpu_ct_save 20,$a0 |
| fpu_ct_save 21,$a0 |
| fpu_ct_save 22,$a0 |
| fpu_ct_save 23,$a0 |
| fpu_ct_save 24,$a0 |
| fpu_ct_save 25,$a0 |
| fpu_ct_save 26,$a0 |
| fpu_ct_save 27,$a0 |
| fpu_ct_save 28,$a0 |
| fpu_ct_save 29,$a0 |
| fpu_ct_save 30,$a0 |
| fpu_ct_save 31,$a0 |
| #endif |
| j $ra |
| nop |
| .global fpu_context_restore |
| fpu_context_restore: |
| #ifdef CONFIG_FPU |
| fpu_gp_restore 0, $a0 |
| fpu_gp_restore 1, $a0 |
| fpu_gp_restore 2, $a0 |
| fpu_gp_restore 3, $a0 |
| fpu_gp_restore 4, $a0 |
| fpu_gp_restore 5, $a0 |
| fpu_gp_restore 6, $a0 |
| fpu_gp_restore 7, $a0 |
| fpu_gp_restore 8, $a0 |
| fpu_gp_restore 9, $a0 |
| fpu_gp_restore 10, $a0 |
| fpu_gp_restore 11, $a0 |
| fpu_gp_restore 12, $a0 |
| fpu_gp_restore 13, $a0 |
| fpu_gp_restore 14, $a0 |
| fpu_gp_restore 15, $a0 |
| fpu_gp_restore 16, $a0 |
| fpu_gp_restore 17, $a0 |
| fpu_gp_restore 18, $a0 |
| fpu_gp_restore 19, $a0 |
| fpu_gp_restore 20, $a0 |
| fpu_gp_restore 21, $a0 |
| fpu_gp_restore 22, $a0 |
| fpu_gp_restore 23, $a0 |
| fpu_gp_restore 24, $a0 |
| fpu_gp_restore 25, $a0 |
| fpu_gp_restore 26, $a0 |
| fpu_gp_restore 27, $a0 |
| fpu_gp_restore 28, $a0 |
| fpu_gp_restore 29, $a0 |
| fpu_gp_restore 30, $a0 |
| fpu_gp_restore 31, $a0 |
| fpu_ct_restore 1, $a0 |
| fpu_ct_restore 2, $a0 |
| fpu_ct_restore 3, $a0 |
| fpu_ct_restore 4, $a0 |
| fpu_ct_restore 5, $a0 |
| fpu_ct_restore 6, $a0 |
| fpu_ct_restore 7, $a0 |
| fpu_ct_restore 8, $a0 |
| fpu_ct_restore 9, $a0 |
| fpu_ct_restore 10, $a0 |
| fpu_ct_restore 11, $a0 |
| fpu_ct_restore 12, $a0 |
| fpu_ct_restore 13, $a0 |
| fpu_ct_restore 14, $a0 |
| fpu_ct_restore 15, $a0 |
| fpu_ct_restore 16, $a0 |
| fpu_ct_restore 17, $a0 |
| fpu_ct_restore 18, $a0 |
| fpu_ct_restore 19, $a0 |
| fpu_ct_restore 20, $a0 |
| fpu_ct_restore 21, $a0 |
| fpu_ct_restore 22, $a0 |
| fpu_ct_restore 23, $a0 |
| fpu_ct_restore 24, $a0 |
| fpu_ct_restore 25, $a0 |
| fpu_ct_restore 26, $a0 |
| fpu_ct_restore 27, $a0 |
| fpu_ct_restore 28, $a0 |
| fpu_ct_restore 29, $a0 |
| fpu_ct_restore 30, $a0 |
| fpu_ct_restore 31, $a0 |
| #endif |
| #ifdef ARCH_HAS_FPU |
| fpu_gp_restore 0,$a0 |
| fpu_gp_restore 1,$a0 |
| fpu_gp_restore 2,$a0 |
| fpu_gp_restore 3,$a0 |
| fpu_gp_restore 4,$a0 |
| fpu_gp_restore 5,$a0 |
| fpu_gp_restore 6,$a0 |
| fpu_gp_restore 7,$a0 |
| fpu_gp_restore 8,$a0 |
| fpu_gp_restore 9,$a0 |
| fpu_gp_restore 10,$a0 |
| fpu_gp_restore 11,$a0 |
| fpu_gp_restore 12,$a0 |
| fpu_gp_restore 13,$a0 |
| fpu_gp_restore 14,$a0 |
| fpu_gp_restore 15,$a0 |
| fpu_gp_restore 16,$a0 |
| fpu_gp_restore 17,$a0 |
| fpu_gp_restore 18,$a0 |
| fpu_gp_restore 19,$a0 |
| fpu_gp_restore 20,$a0 |
| fpu_gp_restore 21,$a0 |
| fpu_gp_restore 22,$a0 |
| fpu_gp_restore 23,$a0 |
| fpu_gp_restore 24,$a0 |
| fpu_gp_restore 25,$a0 |
| fpu_gp_restore 26,$a0 |
| fpu_gp_restore 27,$a0 |
| fpu_gp_restore 28,$a0 |
| fpu_gp_restore 29,$a0 |
| fpu_gp_restore 30,$a0 |
| fpu_gp_restore 31,$a0 |
| fpu_ct_restore 1,$a0 |
| fpu_ct_restore 2,$a0 |
| fpu_ct_restore 3,$a0 |
| fpu_ct_restore 4,$a0 |
| fpu_ct_restore 5,$a0 |
| fpu_ct_restore 6,$a0 |
| fpu_ct_restore 7,$a0 |
| fpu_ct_restore 8,$a0 |
| fpu_ct_restore 9,$a0 |
| fpu_ct_restore 10,$a0 |
| fpu_ct_restore 11,$a0 |
| fpu_ct_restore 12,$a0 |
| fpu_ct_restore 13,$a0 |
| fpu_ct_restore 14,$a0 |
| fpu_ct_restore 15,$a0 |
| fpu_ct_restore 16,$a0 |
| fpu_ct_restore 17,$a0 |
| fpu_ct_restore 18,$a0 |
| fpu_ct_restore 19,$a0 |
| fpu_ct_restore 20,$a0 |
| fpu_ct_restore 21,$a0 |
| fpu_ct_restore 22,$a0 |
| fpu_ct_restore 23,$a0 |
| fpu_ct_restore 24,$a0 |
| fpu_ct_restore 25,$a0 |
| fpu_ct_restore 26,$a0 |
| fpu_ct_restore 27,$a0 |
| fpu_ct_restore 28,$a0 |
| fpu_ct_restore 29,$a0 |
| fpu_ct_restore 30,$a0 |
| fpu_ct_restore 31,$a0 |
| #endif |
| j $ra |
| nop |
| /branches/tracing/kernel/arch/mips32/src/console.c |
|---|
| 0,0 → 1,65 |
| /* |
| * Copyright (c) 2005 Ondrej Palkovsky |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32 |
| * @{ |
| */ |
| /** @file |
| */ |
| #include <console/console.h> |
| #include <arch/console.h> |
| #include <arch/drivers/serial.h> |
| #include <arch/drivers/msim.h> |
| void console_init(devno_t devno) |
| { |
| if (serial_init()) |
| serial_console(devno); |
| else |
| msim_console(devno); |
| } |
| /** Acquire console back for kernel |
| * |
| */ |
| void arch_grab_console(void) |
| { |
| msim_kbd_grab(); |
| } |
| /** Return console to userspace |
| * |
| */ |
| void arch_release_console(void) |
| { |
| msim_kbd_release(); |
| } |
| /** @} |
| */ |
| /branches/tracing/kernel/arch/mips32/src/start.S |
|---|
| 31,7 → 31,7 |
| #include <arch/asm/boot.h> |
| #include <arch/context_offset.h> |
| #include <arch/stack.h> |
| .text |
| .set noat |
| 75,6 → 75,18 |
| mfhi $at |
| sw $at, EOFFSET_HI(\r) |
| #ifdef CONFIG_DEBUG_ALLREGS |
| sw $s0, EOFFSET_S0(\r) |
| sw $s1, EOFFSET_S1(\r) |
| sw $s2, EOFFSET_S2(\r) |
| sw $s3, EOFFSET_S3(\r) |
| sw $s4, EOFFSET_S4(\r) |
| sw $s5, EOFFSET_S5(\r) |
| sw $s6, EOFFSET_S6(\r) |
| sw $s7, EOFFSET_S7(\r) |
| sw $s8, EOFFSET_S8(\r) |
| #endif |
| sw $gp, EOFFSET_GP(\r) |
| sw $ra, EOFFSET_RA(\r) |
| sw $k1, EOFFSET_K1(\r) |
| 120,6 → 132,17 |
| lw $t8, EOFFSET_T8(\r) |
| lw $t9, EOFFSET_T9(\r) |
| #ifdef CONFIG_DEBUG_ALLREGS |
| lw $s0, EOFFSET_S0(\r) |
| lw $s1, EOFFSET_S1(\r) |
| lw $s2, EOFFSET_S2(\r) |
| lw $s3, EOFFSET_S3(\r) |
| lw $s4, EOFFSET_S4(\r) |
| lw $s5, EOFFSET_S5(\r) |
| lw $s6, EOFFSET_S6(\r) |
| lw $s7, EOFFSET_S7(\r) |
| lw $s8, EOFFSET_S8(\r) |
| #endif |
| lw $gp, EOFFSET_GP(\r) |
| lw $ra, EOFFSET_RA(\r) |
| lw $k1, EOFFSET_K1(\r) |
| 152,9 → 175,9 |
| ori $k0, $k0, %lo(supervisor_sp) |
| # Move $k0 (superveisor_sp) |
| lw $k0, 0($k0) |
| 1: |
| 1: |
| .endm |
| .org 0x0 |
| kernel_image_start: |
| /* Load temporary stack */ |
| 161,12 → 184,31 |
| lui $sp, %hi(end_stack) |
| ori $sp, $sp, %lo(end_stack) |
| /* Not sure about this, but might |
| be needed for PIC code */ |
| /* $a1 contains physical address of bootinfo_t */ |
| /* $a2 contains size of bootinfo_t */ |
| beq $a2, $0, bootinfo_end |
| /* Not sure about this, but might be needed for PIC code???? */ |
| lui $gp, 0x8000 |
| /* $a1 contains physical address of bootinfo_t */ |
| lui $a3, %hi(bootinfo) |
| ori $a3, $a3, %lo(bootinfo) |
| bootinfo_loop: |
| lw $v0, 0($a1) |
| sw $v0, 0($a3) |
| addi $a1, $a1, 4 |
| addi $a3, $a3, 4 |
| addi $a2, $a2, -4 |
| bgtz $a2, bootinfo_loop |
| nop |
| bootinfo_end: |
| jal arch_pre_main |
| nop |
| 186,8 → 228,8 |
| exception_entry: |
| j exception_handler |
| nop |
| nop |
| exception_handler: |
| KERNEL_STACK_TO_K0 |
| sub $k0, REGISTER_SPACE |
| 196,17 → 238,17 |
| mfc0 $k0, $cause |
| sra $k0, $k0, 0x2 # cp0_exc_cause() part 1 |
| andi $k0, $k0, 0x1f # cp0_exc_cause() part 2 |
| sub $k0, 8 # 8 = SYSCALL |
| sra $k0, $k0, 0x2 # cp0_exc_cause() part 1 |
| andi $k0, $k0, 0x1f # cp0_exc_cause() part 2 |
| sub $k0, 8 # 8 = SYSCALL |
| beqz $k0, syscall_shortcut |
| add $k0, 8 # Revert $k0 back to correct exc number |
| add $k0, 8 # Revert $k0 back to correct exc number |
| REGISTERS_STORE_AND_EXC_RESET $sp |
| move $a1, $sp |
| jal exc_dispatch # exc_dispatch(excno, register_space) |
| jal exc_dispatch # exc_dispatch(excno, register_space) |
| move $a0, $k0 |
| REGISTERS_LOAD $sp |
| /branches/tracing/kernel/arch/mips32/src/interrupt.c |
|---|
| 41,9 → 41,8 |
| #include <ipc/sysipc.h> |
| #include <ddi/device.h> |
| #define IRQ_COUNT 8 |
| #define TIMER_IRQ 7 |
| #define DORDER_IRQ 5 |
| #define IRQ_COUNT 8 |
| #define TIMER_IRQ 7 |
| function virtual_timer_fnc = NULL; |
| static irq_t timer_irq; |
| 101,12 → 100,12 |
| cp0_compare_write(nextcount); |
| } |
| static irq_ownership_t timer_claim(irq_t *irq) |
| static irq_ownership_t timer_claim(void) |
| { |
| return IRQ_ACCEPT; |
| } |
| static void timer_irq_handler(irq_t *irq) |
| static void timer_irq_handler(irq_t *irq, void *arg, ...) |
| { |
| unsigned long drift; |
| /branches/tracing/kernel/arch/mips32/src/drivers/msim.c |
|---|
| 0,0 → 1,171 |
| /* |
| * Copyright (c) 2005 Ondrej Palkovsky |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32 |
| * @{ |
| */ |
| /** @file |
| */ |
| #include <interrupt.h> |
| #include <ipc/irq.h> |
| #include <console/chardev.h> |
| #include <arch/drivers/msim.h> |
| #include <arch/cp0.h> |
| #include <console/console.h> |
| #include <sysinfo/sysinfo.h> |
| #include <ddi/ddi.h> |
| static parea_t msim_parea; |
| static chardev_t console; |
| static irq_t msim_irq; |
| static void msim_write(chardev_t *dev, const char ch); |
| static void msim_enable(chardev_t *dev); |
| static void msim_disable(chardev_t *dev); |
| static char msim_do_read(chardev_t *dev); |
| static chardev_operations_t msim_ops = { |
| .resume = msim_enable, |
| .suspend = msim_disable, |
| .write = msim_write, |
| .read = msim_do_read, |
| }; |
| /** Putchar that works with MSIM & gxemul */ |
| void msim_write(chardev_t *dev, const char ch) |
| { |
| *((char *) MSIM_VIDEORAM) = ch; |
| } |
| /* Called from getc(). */ |
| void msim_enable(chardev_t *dev) |
| { |
| cp0_unmask_int(MSIM_KBD_IRQ); |
| } |
| /* Called from getc(). */ |
| void msim_disable(chardev_t *dev) |
| { |
| cp0_mask_int(MSIM_KBD_IRQ); |
| } |
| #include <print.h> |
| /** Read character using polling, assume interrupts disabled */ |
| static char msim_do_read(chardev_t *dev) |
| { |
| char ch; |
| while (1) { |
| ch = *((volatile char *) MSIM_KBD_ADDRESS); |
| if (ch) { |
| if (ch == '\r') |
| return '\n'; |
| if (ch == 0x7f) |
| return '\b'; |
| return ch; |
| } |
| } |
| } |
| /** Process keyboard interrupt. */ |
| static void msim_irq_handler(irq_t *irq, void *arg, ...) |
| { |
| if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) |
| ipc_irq_send_notif(irq); |
| else { |
| char ch = 0; |
| ch = *((char *) MSIM_KBD_ADDRESS); |
| if (ch =='\r') |
| ch = '\n'; |
| if (ch == 0x7f) |
| ch = '\b'; |
| chardev_push_character(&console, ch); |
| } |
| } |
| static irq_ownership_t msim_claim(void) |
| { |
| return IRQ_ACCEPT; |
| } |
| void msim_kbd_grab(void) |
| { |
| ipl_t ipl = interrupts_disable(); |
| spinlock_lock(&msim_irq.lock); |
| msim_irq.notif_cfg.notify = false; |
| spinlock_unlock(&msim_irq.lock); |
| interrupts_restore(ipl); |
| } |
| void msim_kbd_release(void) |
| { |
| ipl_t ipl = interrupts_disable(); |
| spinlock_lock(&msim_irq.lock); |
| if (msim_irq.notif_cfg.answerbox) |
| msim_irq.notif_cfg.notify = true; |
| spinlock_unlock(&msim_irq.lock); |
| interrupts_restore(ipl); |
| } |
| /* Return console object representing msim console */ |
| void msim_console(devno_t devno) |
| { |
| chardev_initialize("msim_console", &console, &msim_ops); |
| stdin = &console; |
| stdout = &console; |
| irq_initialize(&msim_irq); |
| msim_irq.devno = devno; |
| msim_irq.inr = MSIM_KBD_IRQ; |
| msim_irq.claim = msim_claim; |
| msim_irq.handler = msim_irq_handler; |
| irq_register(&msim_irq); |
| cp0_unmask_int(MSIM_KBD_IRQ); |
| sysinfo_set_item_val("kbd", NULL, true); |
| sysinfo_set_item_val("kbd.devno", NULL, devno); |
| sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ); |
| sysinfo_set_item_val("kbd.address.virtual", NULL, MSIM_KBD_ADDRESS); |
| msim_parea.pbase = KA2PA(MSIM_VIDEORAM); |
| msim_parea.vbase = MSIM_VIDEORAM; |
| msim_parea.frames = 1; |
| msim_parea.cacheable = false; |
| ddi_parea_register(&msim_parea); |
| sysinfo_set_item_val("fb", NULL, true); |
| sysinfo_set_item_val("fb.kind", NULL, 3); |
| sysinfo_set_item_val("fb.address.physical", NULL, KA2PA(MSIM_VIDEORAM)); |
| } |
| /** @} |
| */ |
| /branches/tracing/kernel/arch/mips32/src/drivers/serial.c |
|---|
| 0,0 → 1,159 |
| /* |
| * Copyright (c) 2005 Ondrej Palkovsky |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32 |
| * @{ |
| */ |
| /** @file |
| */ |
| #include <interrupt.h> |
| #include <arch/cp0.h> |
| #include <ipc/irq.h> |
| #include <arch/drivers/serial.h> |
| #include <console/chardev.h> |
| #include <console/console.h> |
| #define SERIAL_IRQ 2 |
| static irq_t serial_irq; |
| static chardev_t console; |
| static serial_t sconf[SERIAL_MAX]; |
| static bool kb_enabled; |
| static void serial_write(chardev_t *d, const char ch) |
| { |
| serial_t *sd = (serial_t *)d->data; |
| if (ch == '\n') |
| serial_write(d, '\r'); |
| /* Wait until transmit buffer empty */ |
| while (! (SERIAL_READ_LSR(sd->port) & (1<<TRANSMIT_EMPTY_BIT))) |
| ; |
| SERIAL_WRITE(sd->port, ch); |
| } |
| static void serial_enable(chardev_t *d) |
| { |
| kb_enabled = true; |
| } |
| static void serial_disable(chardev_t *d) |
| { |
| kb_enabled = false; |
| } |
| int serial_init(void) |
| { |
| int i = 0; |
| if (SERIAL_READ_LSR(SERIAL_COM1) == 0x60) { |
| sconf[i].port = SERIAL_COM1; |
| sconf[i].irq = SERIAL_COM1_IRQ; |
| /* Enable interrupt on available data */ |
| i++; |
| } |
| return i; |
| } |
| /** Read character from serial port, wait until available */ |
| static char serial_do_read(chardev_t *dev) |
| { |
| serial_t *sd = (serial_t *)dev->data; |
| char ch; |
| while (!(SERIAL_READ_LSR(sd->port) & 1)) |
| ; |
| ch = SERIAL_READ(sd->port); |
| if (ch =='\r') |
| ch = '\n'; |
| return ch; |
| } |
| static void serial_handler(void) |
| { |
| serial_t *sd = (serial_t *) console.data; |
| char ch; |
| if (!(SERIAL_READ_LSR(sd->port) & 1)) |
| return; |
| ch = SERIAL_READ(sd->port); |
| if (ch =='\r') |
| ch = '\n'; |
| chardev_push_character(&console, ch); |
| } |
| /** Process keyboard interrupt. Does not work in simics? */ |
| static void serial_irq_handler(irq_t *irq, void *arg, ...) |
| { |
| if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) |
| ipc_irq_send_notif(irq); |
| else |
| serial_handler(); |
| } |
| static irq_ownership_t serial_claim(void) |
| { |
| return IRQ_ACCEPT; |
| } |
| static chardev_operations_t serial_ops = { |
| .resume = serial_enable, |
| .suspend = serial_disable, |
| .write = serial_write, |
| .read = serial_do_read |
| }; |
| void serial_console(devno_t devno) |
| { |
| serial_t *sd = &sconf[0]; |
| chardev_initialize("serial_console", &console, &serial_ops); |
| console.data = sd; |
| kb_enabled = true; |
| irq_initialize(&serial_irq); |
| serial_irq.devno = devno; |
| serial_irq.inr = SERIAL_IRQ; |
| serial_irq.claim = serial_claim; |
| serial_irq.handler = serial_irq_handler; |
| irq_register(&serial_irq); |
| /* I don't know why, but the serial interrupts simply |
| * don't work on simics |
| */ |
| virtual_timer_fnc = &serial_handler; |
| stdin = &console; |
| stdout = &console; |
| } |
| /** @} |
| */ |
| /branches/tracing/kernel/arch/mips32/src/debugger.c |
|---|
| 37,18 → 37,16 |
| #include <memstr.h> |
| #include <console/kconsole.h> |
| #include <console/cmd.h> |
| #include <symtab.h> |
| #include <print.h> |
| #include <panic.h> |
| #include <arch.h> |
| #include <arch/cp0.h> |
| #include <func.h> |
| #include <symtab.h> |
| bpinfo_t breakpoints[BKPOINTS_MAX]; |
| SPINLOCK_INITIALIZE(bkpoint_lock); |
| #ifdef CONFIG_KCONSOLE |
| static int cmd_print_breakpoints(cmd_arg_t *argv); |
| static cmd_info_t bkpts_info = { |
| .name = "bkpts", |
| 125,12 → 123,10 |
| {0, 0} /* EndOfTable */ |
| }; |
| /** Test, if the given instruction is a jump or branch instruction |
| * |
| * @param instr Instruction code |
| * @return true - it is jump instruction, false otherwise |
| * |
| */ |
| static bool is_jump(unative_t instr) |
| { |
| 162,7 → 158,7 |
| for (i = 0; i < BKPOINTS_MAX; i++) { |
| if (breakpoints[i].address == (uintptr_t)argv->intval) { |
| printf("Duplicate breakpoint %d.\n", i); |
| spinlock_unlock(&bkpoint_lock); |
| spinlock_unlock(&bkpoints_lock); |
| return 0; |
| } else if (breakpoints[i].address == (uintptr_t)argv->intval + |
| sizeof(unative_t) || breakpoints[i].address == |
| 169,10 → 165,10 |
| (uintptr_t)argv->intval - sizeof(unative_t)) { |
| printf("Adjacent breakpoints not supported, conflict " |
| "with %d.\n", i); |
| spinlock_unlock(&bkpoint_lock); |
| spinlock_unlock(&bkpoints_lock); |
| return 0; |
| } |
| } |
| for (i = 0; i < BKPOINTS_MAX; i++) |
| 259,9 → 255,8 |
| for (i = 0; i < BKPOINTS_MAX; i++) |
| if (breakpoints[i].address) { |
| symbol = symtab_fmt_name_lookup( |
| breakpoints[i].address); |
| symbol = get_symtab_entry(breakpoints[i].address); |
| printf("%-2u %-5d %#10zx %-6s %-7s %-8s %s\n", i, |
| breakpoints[i].counter, breakpoints[i].address, |
| ((breakpoints[i].flags & BKPOINT_INPROG) ? "true" : |
| 272,8 → 267,6 |
| return 1; |
| } |
| #endif |
| /** Initialize debugger */ |
| void debugger_init() |
| { |
| 281,24 → 274,22 |
| for (i = 0; i < BKPOINTS_MAX; i++) |
| breakpoints[i].address = NULL; |
| #ifdef CONFIG_KCONSOLE |
| cmd_initialize(&bkpts_info); |
| if (!cmd_register(&bkpts_info)) |
| printf("Cannot register command %s\n", bkpts_info.name); |
| panic("could not register command %s\n", bkpts_info.name); |
| cmd_initialize(&delbkpt_info); |
| if (!cmd_register(&delbkpt_info)) |
| printf("Cannot register command %s\n", delbkpt_info.name); |
| panic("could not register command %s\n", delbkpt_info.name); |
| cmd_initialize(&addbkpt_info); |
| if (!cmd_register(&addbkpt_info)) |
| printf("Cannot register command %s\n", addbkpt_info.name); |
| panic("could not register command %s\n", addbkpt_info.name); |
| cmd_initialize(&addbkpte_info); |
| if (!cmd_register(&addbkpte_info)) |
| printf("Cannot register command %s\n", addbkpte_info.name); |
| #endif |
| panic("could not register command %s\n", addbkpte_info.name); |
| } |
| /** Handle breakpoint |
| 317,7 → 308,7 |
| /* test branch delay slot */ |
| if (cp0_cause_read() & 0x80000000) |
| panic("Breakpoint in branch delay slot not supported."); |
| panic("Breakpoint in branch delay slot not supported.\n"); |
| spinlock_lock(&bkpoint_lock); |
| for (i = 0; i < BKPOINTS_MAX; i++) { |
| 349,10 → 340,9 |
| if (cur->flags & BKPOINT_INPROG) |
| printf("Warning: breakpoint recursion\n"); |
| if (!(cur->flags & BKPOINT_FUNCCALL)) { |
| if (!(cur->flags & BKPOINT_FUNCCALL)) |
| printf("***Breakpoint %d: %p in %s.\n", i, fireaddr, |
| symtab_fmt_name_lookup(istate->epc)); |
| } |
| get_symtab_entry(istate->epc)); |
| /* Return first instruction back */ |
| ((uint32_t *)cur->address)[0] = cur->instruction; |
| 365,9 → 355,8 |
| } |
| cur->flags |= BKPOINT_INPROG; |
| } else { |
| printf("***Breakpoint %d: %p in %s.\n", i, fireaddr, |
| symtab_fmt_name_lookup(fireaddr)); |
| printf("***Breakpoint %p in %s.\n", fireaddr, |
| get_symtab_entry(fireaddr)); |
| /* Move on to next instruction */ |
| istate->epc += 4; |
| } |
| 378,20 → 367,19 |
| if (cur->bkfunc) |
| cur->bkfunc(cur, istate); |
| } else { |
| #ifdef CONFIG_KCONSOLE |
| printf("***Type 'exit' to exit kconsole.\n"); |
| /* This disables all other processors - we are not SMP, |
| * actually this gets us to cpu_halt, if scheduler() is run |
| * - we generally do not want scheduler to be run from debug, |
| * so this is a good idea |
| */ |
| atomic_set(&haltstate, 1); |
| atomic_set(&haltstate,1); |
| spinlock_unlock(&bkpoint_lock); |
| kconsole("debug", "Debug console ready.\n", false); |
| kconsole("debug"); |
| spinlock_lock(&bkpoint_lock); |
| atomic_set(&haltstate, 0); |
| #endif |
| atomic_set(&haltstate,0); |
| } |
| if (cur && cur->address == fireaddr && (cur->flags & BKPOINT_INPROG)) { |
| /* Remove one-shot breakpoint */ |
| /branches/tracing/kernel/arch/mips32/src/cpu/cpu.c |
|---|
| 48,7 → 48,7 |
| { "MIPS", "R2000" }, /* 0x01 */ |
| { "MIPS", "R3000" }, /* 0x02 */ |
| { "MIPS", "R6000" }, /* 0x03 */ |
| { "MIPS", "R4000/R4400" }, /* 0x04 */ |
| { "MIPS", " R4000/R4400" }, /* 0x04 */ |
| { "LSI Logic", "R3000" }, /* 0x05 */ |
| { "MIPS", "R6000A" }, /* 0x06 */ |
| { "IDT", "3051/3052" }, /* 0x07 */ |
| 123,9 → 123,9 |
| data = &imp_data[m->arch.imp_num]; |
| } |
| printf("cpu%u: %s %s (rev=%d.%d, imp=%d)\n", |
| printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n", |
| m->id, data->vendor, data->model, m->arch.rev_num >> 4, |
| m->arch.rev_num & 0x0f, m->arch.imp_num); |
| m->arch.rev_num & 0xf, m->arch.imp_num); |
| } |
| /** @} |
| /branches/tracing/kernel/arch/mips32/src/smp/dorder.c |
|---|
| File deleted |
| /branches/tracing/kernel/arch/mips32/src/smp/smp.c |
|---|
| File deleted |
| /branches/tracing/kernel/arch/mips32/src/smp/order.c |
|---|
| 0,0 → 1,45 |
| /* |
| * Copyright (c) 2007 Martin Decky |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32 |
| * @{ |
| */ |
| /** @file |
| */ |
| #include <arch/smp/order.h> |
| #define MSIM_ORDER_ADDRESS 0xB0000004 |
| void ipi_broadcast_arch(int ipi) |
| { |
| *((volatile unsigned int *) MSIM_ORDER_ADDRESS) = 0x7FFFFFFF; |
| } |
| /** @} |
| */ |
| /branches/tracing/kernel/arch/mips32/src/cache.c |
|---|
| 38,7 → 38,7 |
| void cache_error(istate_t *istate) |
| { |
| panic("cache_error exception (epc=%p).", istate->epc); |
| panic("cache_error exception (epc=%p)\n", istate->epc); |
| } |
| /** @} |
| /branches/tracing/kernel/arch/mips32/src/fpu_context.c |
|---|
| 40,7 → 40,7 |
| void fpu_disable(void) |
| { |
| #ifdef CONFIG_FPU |
| #ifdef ARCH_HAS_FPU |
| cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit); |
| #endif |
| } |
| 47,7 → 47,7 |
| void fpu_enable(void) |
| { |
| #ifdef CONFIG_FPU |
| #ifdef ARCH_HAS_FPU |
| cp0_status_write(cp0_status_read() | cp0_status_fpu_bit); |
| #endif |
| } |
| /branches/tracing/kernel/arch/mips32/src/dummy.S |
|---|
| 0,0 → 1,41 |
| # |
| # Copyright (c) 2003-2004 Jakub Jermar |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions |
| # are met: |
| # |
| # - Redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer. |
| # - Redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution. |
| # - The name of the author may not be used to endorse or promote products |
| # derived from this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| .text |
| .set noat |
| .global calibrate_delay_loop |
| .global asm_delay_loop |
| .global dummy |
| calibrate_delay_loop: |
| asm_delay_loop: |
| dummy: |
| j $31 |
| nop |