| /branches/tracing/kernel/arch/mips32/include/console.h |
|---|
| File deleted |
| /branches/tracing/kernel/arch/mips32/include/boot.h |
|---|
| File deleted |
| /branches/tracing/kernel/arch/mips32/include/asm/boot.h |
|---|
| 26,7 → 26,7 |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32 |
| /** @addtogroup mips32 |
| * @{ |
| */ |
| /** @file |
| /branches/tracing/kernel/arch/mips32/include/context_offset.h |
|---|
| 76,26 → 76,17 |
| #define EOFFSET_T5 0x30 |
| #define EOFFSET_T6 0x34 |
| #define EOFFSET_T7 0x38 |
| #define EOFFSET_S0 0x3c |
| #define EOFFSET_S1 0x40 |
| #define EOFFSET_S2 0x44 |
| #define EOFFSET_S3 0x48 |
| #define EOFFSET_S4 0x4c |
| #define EOFFSET_S5 0x50 |
| #define EOFFSET_S6 0x54 |
| #define EOFFSET_S7 0x58 |
| #define EOFFSET_T8 0x5c |
| #define EOFFSET_T9 0x60 |
| #define EOFFSET_GP 0x64 |
| #define EOFFSET_SP 0x68 |
| #define EOFFSET_S8 0x6c |
| #define EOFFSET_RA 0x70 |
| #define EOFFSET_LO 0x74 |
| #define EOFFSET_HI 0x78 |
| #define EOFFSET_STATUS 0x7c |
| #define EOFFSET_EPC 0x80 |
| #define EOFFSET_K1 0x84 |
| #define REGISTER_SPACE 136 |
| #define EOFFSET_T8 0x3c |
| #define EOFFSET_T9 0x40 |
| #define EOFFSET_GP 0x44 |
| #define EOFFSET_SP 0x48 |
| #define EOFFSET_RA 0x4c |
| #define EOFFSET_LO 0x50 |
| #define EOFFSET_HI 0x54 |
| #define EOFFSET_STATUS 0x58 |
| #define EOFFSET_EPC 0x5c |
| #define EOFFSET_K1 0x60 |
| #define REGISTER_SPACE 100 |
| #ifdef __ASM__ |
| 114,10 → 105,10 |
| sw $s8,OFFSET_S8(\ctx) |
| sw $gp,OFFSET_GP(\ctx) |
| #ifndef KERNEL |
| #ifndef KERNEL |
| sw $k1,OFFSET_TLS(\ctx) |
| # ifdef CONFIG_MIPS_FPU |
| #ifdef CONFIG_FPU |
| mfc1 $t0,$20 |
| sw $t0, OFFSET_F20(\ctx) |
| 150,7 → 141,7 |
| mfc1 $t0,$30 |
| sw $t0, OFFSET_F30(\ctx) |
| # endif /* CONFIG_MIPS_FPU */ |
| #endif /* CONFIG_FPU */ |
| #endif /* KERNEL */ |
| sw $ra,OFFSET_PC(\ctx) |
| 172,7 → 163,7 |
| #ifndef KERNEL |
| lw $k1,OFFSET_TLS(\ctx) |
| # ifdef CONFIG_MIPS_FPU |
| #ifdef CONFIG_FPU |
| lw $t0, OFFSET_F20(\ctx) |
| mtc1 $t0,$20 |
| 205,9 → 196,9 |
| lw $t0, OFFSET_F30(\ctx) |
| mtc1 $t0,$30 |
| # endif /* CONFIG_MIPS_FPU */ |
| #endif /* CONFIG_FPU */ |
| #endif /* KERNEL */ |
| lw $ra,OFFSET_PC(\ctx) |
| lw $sp,OFFSET_SP(\ctx) |
| .endm |
| /branches/tracing/kernel/arch/mips32/include/interrupt.h |
|---|
| 38,9 → 38,11 |
| #include <typedefs.h> |
| #include <arch/exception.h> |
| #define IVT_ITEMS 32 |
| #define IVT_FIRST 0 |
| #define IVT_ITEMS 32 |
| #define IVT_FIRST 0 |
| #define VECTOR_TLB_SHOOTDOWN_IPI EXC_Int |
| extern function virtual_timer_fnc; |
| extern uint32_t count_hi; |
| /branches/tracing/kernel/arch/mips32/include/exception.h |
|---|
| 73,19 → 73,10 |
| uint32_t t5; |
| uint32_t t6; |
| uint32_t t7; |
| uint32_t s0; |
| uint32_t s1; |
| uint32_t s2; |
| uint32_t s3; |
| uint32_t s4; |
| uint32_t s5; |
| uint32_t s6; |
| uint32_t s7; |
| uint32_t t8; |
| uint32_t t9; |
| uint32_t gp; |
| uint32_t sp; |
| uint32_t s8; |
| uint32_t ra; |
| uint32_t lo; |
| /branches/tracing/kernel/arch/mips32/include/types.h |
|---|
| 57,6 → 57,9 |
| typedef uint32_t unative_t; |
| typedef int32_t native_t; |
| typedef struct { |
| } fncptr_t; |
| #define PRIp "x" /**< Format for uintptr_t. */ |
| #define PRIs "u" /**< Format for size_t. */ |
| #define PRIc "u" /**< Format for count_t. */ |
| /branches/tracing/kernel/arch/mips32/include/elf.h |
|---|
| 35,9 → 35,11 |
| #ifndef KERN_mips32_ELF_H_ |
| #define KERN_mips32_ELF_H_ |
| #include <byteorder.h> |
| #define ELF_MACHINE EM_MIPS |
| #ifdef BIG_ENDIAN |
| #ifdef ARCH_IS_BIG_ENDIAN |
| # define ELF_DATA_ENCODING ELFDATA2MSB |
| #else |
| # define ELF_DATA_ENCODING ELFDATA2LSB |
| /branches/tracing/kernel/arch/mips32/include/smp/order.h |
|---|
| File deleted |
| /branches/tracing/kernel/arch/mips32/include/smp/dorder.h |
|---|
| 0,0 → 1,34 |
| /* |
| * Copyright (c) 2007 Martin Decky |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| #ifndef KERN_mips32_DORDER_H_ |
| #define KERN_mips32_DORDER_H_ |
| extern void ipi_broadcast_arch(int ipi); |
| #endif |
| /branches/tracing/kernel/arch/mips32/include/atomic.h |
|---|
| 35,14 → 35,14 |
| #ifndef KERN_mips32_ATOMIC_H_ |
| #define KERN_mips32_ATOMIC_H_ |
| #define atomic_inc(x) ((void) atomic_add(x, 1)) |
| #define atomic_dec(x) ((void) atomic_add(x, -1)) |
| #define atomic_inc(x) ((void) atomic_add(x, 1)) |
| #define atomic_dec(x) ((void) atomic_add(x, -1)) |
| #define atomic_postinc(x) (atomic_add(x, 1) - 1) |
| #define atomic_postdec(x) (atomic_add(x, -1) + 1) |
| #define atomic_postinc(x) (atomic_add(x, 1) - 1) |
| #define atomic_postdec(x) (atomic_add(x, -1) + 1) |
| #define atomic_preinc(x) atomic_add(x, 1) |
| #define atomic_predec(x) atomic_add(x, -1) |
| #define atomic_preinc(x) atomic_add(x, 1) |
| #define atomic_predec(x) atomic_add(x, -1) |
| /* Atomic addition of immediate value. |
| * |
| 54,19 → 54,37 |
| static inline long atomic_add(atomic_t *val, int i) |
| { |
| long tmp, v; |
| asm volatile ( |
| "1:\n" |
| " ll %0, %1\n" |
| " addu %0, %0, %3\n" /* same as addi, but never traps on overflow */ |
| " move %2, %0\n" |
| " addu %0, %0, %3\n" /* same as addi, but never traps on overflow */ |
| " move %2, %0\n" |
| " sc %0, %1\n" |
| " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */ |
| " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */ |
| " nop\n" |
| : "=&r" (tmp), "+m" (val->count), "=&r" (v) |
| : "r" (i), "i" (0) |
| ); |
| ); |
| return v; |
| } |
| static inline uint32_t test_and_set(atomic_t *val) { |
| uint32_t tmp, v; |
| asm volatile ( |
| "1:\n" |
| " ll %2, %1\n" |
| " bnez %2, 2f\n" |
| " li %0, %3\n" |
| " sc %0, %1\n" |
| " beqz %0, 1b\n" |
| "2:\n" |
| : "=&r" (tmp), "+m" (val->count), "=&r" (v) |
| : "i" (1) |
| ); |
| return v; |
| } |
| /branches/tracing/kernel/arch/mips32/include/arch.h |
|---|
| 26,7 → 26,7 |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32 |
| /** @addtogroup mips32 |
| * @{ |
| */ |
| /** @file |
| 35,6 → 35,29 |
| #ifndef KERN_mips32_ARCH_H_ |
| #define KERN_mips32_ARCH_H_ |
| #define TASKMAP_MAX_RECORDS 32 |
| #define CPUMAP_MAX_RECORDS 32 |
| #define BOOTINFO_TASK_NAME_BUFLEN 32 |
| #include <typedefs.h> |
| extern count_t cpu_count; |
| typedef struct { |
| uintptr_t addr; |
| uint32_t size; |
| char name[BOOTINFO_TASK_NAME_BUFLEN]; |
| } utask_t; |
| typedef struct { |
| uint32_t cpumap; |
| uint32_t cnt; |
| utask_t tasks[TASKMAP_MAX_RECORDS]; |
| } bootinfo_t; |
| extern void arch_pre_main(void *entry, bootinfo_t *bootinfo); |
| #endif |
| /** @} |
| /branches/tracing/kernel/arch/mips32/include/asm.h |
|---|
| 36,6 → 36,7 |
| #define KERN_mips32_ASM_H_ |
| #include <arch/types.h> |
| #include <typedefs.h> |
| #include <config.h> |
| 55,7 → 56,11 |
| { |
| uintptr_t v; |
| asm volatile ("and %0, $29, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
| asm volatile ( |
| "and %0, $29, %1\n" |
| : "=r" (v) |
| : "r" (~(STACK_SIZE-1)) |
| ); |
| return v; |
| } |
| 63,13 → 68,44 |
| extern void cpu_halt(void); |
| extern void asm_delay_loop(uint32_t t); |
| extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, |
| uintptr_t entry); |
| uintptr_t entry); |
| extern ipl_t interrupts_disable(void); |
| extern ipl_t interrupts_enable(void); |
| extern void interrupts_restore(ipl_t ipl); |
| extern ipl_t interrupts_read(void); |
| extern void asm_delay_loop(uint32_t t); |
| static inline void pio_write_8(ioport8_t *port, uint8_t v) |
| { |
| *port = v; |
| } |
| static inline void pio_write_16(ioport16_t *port, uint16_t v) |
| { |
| *port = v; |
| } |
| static inline void pio_write_32(ioport32_t *port, uint32_t v) |
| { |
| *port = v; |
| } |
| static inline uint8_t pio_read_8(ioport8_t *port) |
| { |
| return *port; |
| } |
| static inline uint16_t pio_read_16(ioport16_t *port) |
| { |
| return *port; |
| } |
| static inline uint32_t pio_read_32(ioport32_t *port) |
| { |
| return *port; |
| } |
| #endif |
| /** @} |
| /branches/tracing/kernel/arch/mips32/include/mm/frame.h |
|---|
| 26,7 → 26,7 |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32mm |
| /** @addtogroup mips32mm |
| * @{ |
| */ |
| /** @file |
| 35,12 → 35,14 |
| #ifndef KERN_mips32_FRAME_H_ |
| #define KERN_mips32_FRAME_H_ |
| #define FRAME_WIDTH 14 /* 16K */ |
| #define FRAME_SIZE (1 << FRAME_WIDTH) |
| #define FRAME_WIDTH 14 /* 16K */ |
| #define FRAME_SIZE (1 << FRAME_WIDTH) |
| #ifdef KERNEL |
| #ifndef __ASM__ |
| #include <typedefs.h> |
| extern void frame_arch_init(void); |
| extern void physmem_print(void); |
| /branches/tracing/kernel/arch/mips32/include/mm/asid.h |
|---|
| 37,7 → 37,7 |
| #include <arch/types.h> |
| #define ASID_MAX_ARCH 255 /* 2^8 - 1 */ |
| #define ASID_MAX_ARCH 255 /* 2^8 - 1 */ |
| typedef uint8_t asid_t; |
| /branches/tracing/kernel/arch/mips32/include/mm/tlb.h |
|---|
| 26,7 → 26,7 |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32mm |
| /** @addtogroup mips32mm |
| * @{ |
| */ |
| /** @file |
| 40,42 → 40,38 |
| #include <arch/mm/asid.h> |
| #include <arch/exception.h> |
| #ifdef TLBCNT |
| # define TLB_ENTRY_COUNT TLBCNT |
| #else |
| # define TLB_ENTRY_COUNT 48 |
| #endif |
| #define TLB_ENTRY_COUNT 48 |
| #define TLB_WIRED 1 |
| #define TLB_KSTACK_WIRED_INDEX 0 |
| #define TLB_WIRED 1 |
| #define TLB_KSTACK_WIRED_INDEX 0 |
| #define TLB_PAGE_MASK_4K (0x000 << 13) |
| #define TLB_PAGE_MASK_16K (0x003 << 13) |
| #define TLB_PAGE_MASK_64K (0x00f << 13) |
| #define TLB_PAGE_MASK_256K (0x03f << 13) |
| #define TLB_PAGE_MASK_1M (0x0ff << 13) |
| #define TLB_PAGE_MASK_4M (0x3ff << 13) |
| #define TLB_PAGE_MASK_16M (0xfff << 13) |
| #define TLB_PAGE_MASK_4K (0x000 << 13) |
| #define TLB_PAGE_MASK_16K (0x003 << 13) |
| #define TLB_PAGE_MASK_64K (0x00f << 13) |
| #define TLB_PAGE_MASK_256K (0x03f << 13) |
| #define TLB_PAGE_MASK_1M (0x0ff << 13) |
| #define TLB_PAGE_MASK_4M (0x3ff << 13) |
| #define TLB_PAGE_MASK_16M (0xfff << 13) |
| #define PAGE_UNCACHED 2 |
| #define PAGE_CACHEABLE_EXC_WRITE 5 |
| #define PAGE_UNCACHED 2 |
| #define PAGE_CACHEABLE_EXC_WRITE 5 |
| typedef union { |
| struct { |
| #ifdef BIG_ENDIAN |
| unsigned : 2; /* zero */ |
| unsigned pfn : 24; /* frame number */ |
| unsigned c : 3; /* cache coherency attribute */ |
| unsigned d : 1; /* dirty/write-protect bit */ |
| unsigned v : 1; /* valid bit */ |
| unsigned g : 1; /* global bit */ |
| unsigned : 2; /* zero */ |
| unsigned pfn : 24; /* frame number */ |
| unsigned c : 3; /* cache coherency attribute */ |
| unsigned d : 1; /* dirty/write-protect bit */ |
| unsigned v : 1; /* valid bit */ |
| unsigned g : 1; /* global bit */ |
| #else |
| unsigned g : 1; /* global bit */ |
| unsigned v : 1; /* valid bit */ |
| unsigned d : 1; /* dirty/write-protect bit */ |
| unsigned c : 3; /* cache coherency attribute */ |
| unsigned pfn : 24; /* frame number */ |
| unsigned : 2; /* zero */ |
| unsigned g : 1; /* global bit */ |
| unsigned v : 1; /* valid bit */ |
| unsigned d : 1; /* dirty/write-protect bit */ |
| unsigned c : 3; /* cache coherency attribute */ |
| unsigned pfn : 24; /* frame number */ |
| unsigned : 2; /* zero */ |
| #endif |
| } __attribute__ ((packed)); |
| uint32_t value; |
| 163,7 → 159,7 |
| asm volatile ("tlbwr\n\t"); |
| } |
| #define tlb_invalidate(asid) tlb_invalidate_asid(asid) |
| #define tlb_invalidate(asid) tlb_invalidate_asid(asid) |
| extern void tlb_invalid(istate_t *istate); |
| extern void tlb_refill(istate_t *istate); |
| /branches/tracing/kernel/arch/mips32/include/cpu.h |
|---|
| 42,7 → 42,7 |
| uint32_t imp_num; |
| uint32_t rev_num; |
| } cpu_arch_t; |
| #endif |
| /** @} |
| /branches/tracing/kernel/arch/mips32/include/drivers/serial.h |
|---|
| File deleted |
| /branches/tracing/kernel/arch/mips32/include/drivers/msim.h |
|---|
| 26,7 → 26,7 |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup mips32 |
| /** @addtogroup mips32 |
| * @{ |
| */ |
| /** @file |
| 36,16 → 36,10 |
| #define KERN_mips32_MSIM_H_ |
| /** Address of devices. */ |
| #define MSIM_VIDEORAM 0x90000000 |
| #define MSIM_KBD_ADDRESS 0x90000000 |
| #define MSIM_KBD_IRQ 2 |
| #define MSIM_VIDEORAM 0x90000000 |
| #define MSIM_KBD_ADDRESS 0x90000000 |
| #define MSIM_KBD_IRQ 2 |
| #include <console/chardev.h> |
| void msim_console(devno_t devno); |
| void msim_kbd_release(void); |
| void msim_kbd_grab(void); |
| #endif |
| /** @} |