| 26,7 → 26,7 |
|---|
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| /** @addtogroup ia32 |
| /** @addtogroup ia32 |
| * @{ |
| */ |
| /** @file |
| 112,7 → 112,7 |
|---|
| |
| void tss_initialize(tss_t *t) |
| { |
| memsetb(t, sizeof(struct tss), 0); |
| memsetb(t, sizeof(tss_t), 0); |
| } |
| |
| /* |
| 127,7 → 127,7 |
|---|
| d = &idt[i]; |
| |
| d->unused = 0; |
| d->selector = selector(KTEXT_DES); |
| d->selector = gdtselector(KTEXT_DES); |
| |
| d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
| |
| 154,7 → 154,7 |
|---|
| "and $0xffff8fff, %%eax\n" |
| "push %%eax\n" |
| "popfl\n" |
| : : : "eax" |
| ::: "eax" |
| ); |
| } |
| |
| 165,7 → 165,7 |
|---|
| "mov %%cr0, %%eax\n" |
| "and $0xfffbffff, %%eax\n" |
| "mov %%eax, %%cr0\n" |
| : : : "eax" |
| ::: "eax" |
| ); |
| } |
| |
| 198,7 → 198,7 |
|---|
| else { |
| tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
| if (!tss_p) |
| panic("could not allocate TSS\n"); |
| panic("Cannot allocate TSS."); |
| } |
| |
| tss_initialize(tss_p); |
| 214,7 → 214,7 |
|---|
| * As of this moment, the current CPU has its own GDT pointing |
| * to its own TSS. We just need to load the TR register. |
| */ |
| tr_load(selector(TSS_DES)); |
| tr_load(gdtselector(TSS_DES)); |
| |
| clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ |
| clean_AM_flag(); /* Disable alignment check */ |
| 232,28 → 232,5 |
|---|
| gdtr_load(&cpugdtr); |
| } |
| |
| /* Reboot the machine by initiating |
| * a triple fault |
| */ |
| void arch_reboot(void) |
| { |
| preemption_disable(); |
| ipl_t ipl = interrupts_disable(); |
| |
| memsetb(idt, sizeof(idt), 0); |
| |
| ptr_16_32_t idtr; |
| idtr.limit = sizeof(idt); |
| idtr.base = (uintptr_t) idt; |
| idtr_load(&idtr); |
| |
| interrupts_restore(ipl); |
| asm volatile ( |
| "int $0x03\n" |
| "cli\n" |
| "hlt\n" |
| ); |
| } |
| |
| /** @} |
| */ |