/branches/tracing/kernel/arch/ia32/src/smp/mps.c |
---|
86,10 → 86,10 |
/* |
* Implementation of IA-32 SMP configuration interface. |
*/ |
static count_t get_cpu_count(void); |
static bool is_cpu_enabled(index_t i); |
static bool is_bsp(index_t i); |
static uint8_t get_cpu_apic_id(index_t i); |
static size_t get_cpu_count(void); |
static bool is_cpu_enabled(size_t i); |
static bool is_bsp(size_t i); |
static uint8_t get_cpu_apic_id(size_t i); |
static int mps_irq_to_pin(unsigned int irq); |
struct smp_config_operations mps_config_operations = { |
100,24 → 100,24 |
.irq_to_pin = mps_irq_to_pin |
}; |
count_t get_cpu_count(void) |
size_t get_cpu_count(void) |
{ |
return processor_entry_cnt; |
} |
bool is_cpu_enabled(index_t i) |
bool is_cpu_enabled(size_t i) |
{ |
ASSERT(i < processor_entry_cnt); |
return (bool) ((processor_entries[i].cpu_flags & 0x01) == 0x01); |
} |
bool is_bsp(index_t i) |
bool is_bsp(size_t i) |
{ |
ASSERT(i < processor_entry_cnt); |
return (bool) ((processor_entries[i].cpu_flags & 0x02) == 0x02); |
} |
uint8_t get_cpu_apic_id(index_t i) |
uint8_t get_cpu_apic_id(size_t i) |
{ |
ASSERT(i < processor_entry_cnt); |
return processor_entries[i].l_apic_id; |
/branches/tracing/kernel/arch/ia32/src/ddi/ddi.c |
---|
57,7 → 57,7 |
*/ |
int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) |
{ |
count_t bits; |
size_t bits; |
bits = ioaddr + size; |
if (bits > IO_PORTS) |
99,7 → 99,7 |
/* |
* Enable the range and we are done. |
*/ |
bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size); |
bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size); |
/* |
* Increment I/O Permission bitmap generation counter. |
118,10 → 118,10 |
*/ |
void io_perm_bitmap_install(void) |
{ |
count_t bits; |
size_t bits; |
ptr_16_32_t cpugdtr; |
descriptor_t *gdt_p; |
count_t ver; |
size_t ver; |
/* First, copy the I/O Permission Bitmap. */ |
spinlock_lock(&TASK->lock); |
/branches/tracing/kernel/arch/ia32/src/mm/tlb.c |
---|
59,7 → 59,7 |
* @param page Address of the first page whose entry is to be invalidated. |
* @param cnt Number of entries to invalidate. |
*/ |
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, count_t cnt) |
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt) |
{ |
unsigned int i; |
/branches/tracing/kernel/arch/ia32/src/mm/frame.c |
---|
70,7 → 70,7 |
#endif |
pfn_t pfn; |
count_t count; |
size_t count; |
if (e820table[i].type == MEMMAP_MEMORY_AVAILABLE) { |
/* To be safe, make available zone possibly smaller */ |
/branches/tracing/kernel/arch/ia32/src/interrupt.c |
---|
101,7 → 101,7 |
static void gp_fault(int n __attribute__((unused)), istate_t *istate) |
{ |
if (TASK) { |
count_t ver; |
size_t ver; |
spinlock_lock(&TASK->lock); |
ver = TASK->arch.iomapver; |
/branches/tracing/kernel/arch/ia32/src/atomic.S |
---|
42,9 → 42,7 |
movl 12(%esp),%ebx |
0: |
#ifdef CONFIG_HT |
pause # Pentium 4's with HT love this instruction |
#endif |
movl (%ebx),%eax |
testl %eax,%eax |
jnz 0b # lightweight looping while it is locked |
/branches/tracing/kernel/arch/ia32/src/drivers/vesa.c |
---|
85,15 → 85,15 |
if ((vesa_red_mask == 5) && (vesa_red_pos == 10) |
&& (vesa_green_mask == 5) && (vesa_green_pos == 5) |
&& (vesa_blue_mask == 5) && (vesa_blue_pos == 0)) |
visual = VISUAL_RGB_5_5_5; |
visual = VISUAL_RGB_5_5_5_LE; |
else |
visual = VISUAL_RGB_5_6_5; |
visual = VISUAL_RGB_5_6_5_LE; |
break; |
case 24: |
visual = VISUAL_RGB_8_8_8; |
visual = VISUAL_BGR_8_8_8; |
break; |
case 32: |
visual = VISUAL_RGB_0_8_8_8; |
visual = VISUAL_BGR_8_8_8_0; |
break; |
default: |
panic("Unsupported bits per pixel."); |