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Ignore whitespace Rev 3423 → Rev 3424

/branches/tracing/kernel/arch/ia32/include/types.h
35,10 → 35,6
#ifndef KERN_ia32_TYPES_H_
#define KERN_ia32_TYPES_H_
 
#define NULL 0
#define false 0
#define true 1
 
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed long int32_t;
61,14 → 57,29
typedef uint32_t unative_t;
typedef int32_t native_t;
 
typedef uint8_t bool;
typedef uint64_t thread_id_t;
typedef uint64_t task_id_t;
typedef uint32_t context_id_t;
#define PRIp "x" /**< Format for uintptr_t. */
#define PRIs "u" /**< Format for size_t. */
#define PRIc "u" /**< Format for count_t. */
#define PRIi "u" /**< Format for index_t. */
 
typedef int32_t inr_t;
typedef int32_t devno_t;
#define PRId8 "d" /**< Format for int8_t. */
#define PRId16 "d" /**< Format for int16_t. */
#define PRId32 "d" /**< Format for int32_t. */
#define PRId64 "lld" /**< Format for int64_t. */
#define PRIdn "d" /**< Format for native_t. */
 
#define PRIu8 "u" /**< Format for uint8_t. */
#define PRIu16 "u" /**< Format for uint16_t. */
#define PRIu32 "u" /**< Format for uint32_t. */
#define PRIu64 "llu" /**< Format for uint64_t. */
#define PRIun "u" /**< Format for unative_t. */
 
#define PRIx8 "x" /**< Format for hexadecimal (u)int8_t. */
#define PRIx16 "x" /**< Format for hexadecimal (u)int16_t. */
#define PRIx32 "x" /**< Format for hexadecimal (u)uint32_t. */
#define PRIx64 "llx" /**< Format for hexadecimal (u)int64_t. */
#define PRIxn "x" /**< Format for hexadecimal (u)native_t. */
 
/** Page Table Entry. */
typedef struct {
unsigned present : 1;
/branches/tracing/kernel/arch/ia32/include/memstr.h
35,116 → 35,13
#ifndef KERN_ia32_MEMSTR_H_
#define KERN_ia32_MEMSTR_H_
 
/** Copy memory
*
* Copy a given number of bytes (3rd argument)
* from the memory location defined by 2nd argument
* to the memory location defined by 1st argument.
* The memory areas cannot overlap.
*
* @param dst Destination
* @param src Source
* @param cnt Number of bytes
* @return Destination
*/
static inline void * memcpy(void * dst, const void * src, size_t cnt)
{
unative_t d0, d1, d2;
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt))
 
asm volatile(
/* copy all full dwords */
"rep movsl\n\t"
/* load count again */
"movl %4, %%ecx\n\t"
/* ecx = ecx mod 4 */
"andl $3, %%ecx\n\t"
/* are there last <=3 bytes? */
"jz 1f\n\t"
/* copy last <=3 bytes */
"rep movsb\n\t"
/* exit from asm block */
"1:\n"
: "=&c" (d0), "=&D" (d1), "=&S" (d2)
: "0" ((unative_t) (cnt / 4)), "g" ((unative_t) cnt), "1" ((unative_t) dst), "2" ((unative_t) src)
: "memory");
extern void memsetw(void *dst, size_t cnt, uint16_t x);
extern void memsetb(void *dst, size_t cnt, uint8_t x);
 
return dst;
}
extern int memcmp(const void *a, const void *b, size_t cnt);
 
 
/** Compare memory regions for equality
*
* Compare a given number of bytes (3rd argument)
* at memory locations defined by 1st and 2nd argument
* for equality. If bytes are equal function returns 0.
*
* @param src Region 1
* @param dst Region 2
* @param cnt Number of bytes
* @return Zero if bytes are equal, non-zero otherwise
*/
static inline int memcmp(const void * src, const void * dst, size_t cnt)
{
uint32_t d0, d1, d2;
int ret;
asm (
"repe cmpsb\n\t"
"je 1f\n\t"
"movl %3, %0\n\t"
"addl $1, %0\n\t"
"1:\n"
: "=a" (ret), "=&S" (d0), "=&D" (d1), "=&c" (d2)
: "0" (0), "1" ((unative_t) src), "2" ((unative_t) dst), "3" ((unative_t) cnt)
);
return ret;
}
 
/** Fill memory with words
* Fill a given number of words (2nd argument)
* at memory defined by 1st argument with the
* word value defined by 3rd argument.
*
* @param dst Destination
* @param cnt Number of words
* @param x Value to fill
*/
static inline void memsetw(uintptr_t dst, size_t cnt, uint16_t x)
{
uint32_t d0, d1;
asm volatile (
"rep stosw\n\t"
: "=&D" (d0), "=&c" (d1), "=&a" (x)
: "0" (dst), "1" (cnt), "2" (x)
: "memory"
);
 
}
 
/** Fill memory with bytes
* Fill a given number of bytes (2nd argument)
* at memory defined by 1st argument with the
* word value defined by 3rd argument.
*
* @param dst Destination
* @param cnt Number of bytes
* @param x Value to fill
*/
static inline void memsetb(uintptr_t dst, size_t cnt, uint8_t x)
{
uint32_t d0, d1;
asm volatile (
"rep stosb\n\t"
: "=&D" (d0), "=&c" (d1), "=&a" (x)
: "0" (dst), "1" (cnt), "2" (x)
: "memory"
);
 
}
 
#endif
 
/** @}
/branches/tracing/kernel/arch/ia32/include/smp/apic.h
105,8 → 105,8
#define MODEL_CLUSTER 0x0
 
/** Interrupt Command Register. */
#define ICRlo (0x300/sizeof(uint32_t))
#define ICRhi (0x310/sizeof(uint32_t))
#define ICRlo (0x300 / sizeof(uint32_t))
#define ICRhi (0x310 / sizeof(uint32_t))
typedef struct {
union {
uint32_t lo;
133,10 → 133,10
} __attribute__ ((packed)) icr_t;
 
/* End Of Interrupt. */
#define EOI (0x0b0/sizeof(uint32_t))
#define EOI (0x0b0 / sizeof(uint32_t))
 
/** Error Status Register. */
#define ESR (0x280/sizeof(uint32_t))
#define ESR (0x280 / sizeof(uint32_t))
typedef union {
uint32_t value;
uint8_t err_bitmap;
154,7 → 154,7
} esr_t;
 
/* Task Priority Register */
#define TPR (0x080/sizeof(uint32_t))
#define TPR (0x080 / sizeof(uint32_t))
typedef union {
uint32_t value;
struct {
164,7 → 164,7
} tpr_t;
 
/** Spurious-Interrupt Vector Register. */
#define SVR (0x0f0/sizeof(uint32_t))
#define SVR (0x0f0 / sizeof(uint32_t))
typedef union {
uint32_t value;
struct {
176,7 → 176,7
} svr_t;
 
/** Time Divide Configuration Register. */
#define TDCR (0x3e0/sizeof(uint32_t))
#define TDCR (0x3e0 / sizeof(uint32_t))
typedef union {
uint32_t value;
struct {
186,13 → 186,13
} tdcr_t;
 
/* Initial Count Register for Timer */
#define ICRT (0x380/sizeof(uint32_t))
#define ICRT (0x380 / sizeof(uint32_t))
 
/* Current Count Register for Timer */
#define CCRT (0x390/sizeof(uint32_t))
#define CCRT (0x390 / sizeof(uint32_t))
 
/** LVT Timer register. */
#define LVT_Tm (0x320/sizeof(uint32_t))
#define LVT_Tm (0x320 / sizeof(uint32_t))
typedef union {
uint32_t value;
struct {
207,8 → 207,8
} lvt_tm_t;
 
/** LVT LINT registers. */
#define LVT_LINT0 (0x350/sizeof(uint32_t))
#define LVT_LINT1 (0x360/sizeof(uint32_t))
#define LVT_LINT0 (0x350 / sizeof(uint32_t))
#define LVT_LINT1 (0x360 / sizeof(uint32_t))
typedef union {
uint32_t value;
struct {
225,7 → 225,7
} lvt_lint_t;
 
/** LVT Error register. */
#define LVT_Err (0x370/sizeof(uint32_t))
#define LVT_Err (0x370 / sizeof(uint32_t))
typedef union {
uint32_t value;
struct {
239,7 → 239,7
} lvt_error_t;
 
/** Local APIC ID Register. */
#define L_APIC_ID (0x020/sizeof(uint32_t))
#define L_APIC_ID (0x020 / sizeof(uint32_t))
typedef union {
uint32_t value;
struct {
249,14 → 249,14
} l_apic_id_t;
 
/** Local APIC Version Register */
#define LAVR (0x030/sizeof(uint32_t))
#define LAVR (0x030 / sizeof(uint32_t))
#define LAVR_Mask 0xff
#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1)
#define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0))
#define is_local_xapic(x) (((x)&LAVR_Mask)==0x14)
#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1)
#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0))
#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14)
 
/** Logical Destination Register. */
#define LDR (0x0d0/sizeof(uint32_t))
#define LDR (0x0d0 / sizeof(uint32_t))
typedef union {
uint32_t value;
struct {
266,7 → 266,7
} ldr_t;
 
/** Destination Format Register. */
#define DFR (0x0e0/sizeof(uint32_t))
#define DFR (0x0e0 / sizeof(uint32_t))
typedef union {
uint32_t value;
struct {
276,8 → 276,8
} dfr_t;
 
/* IO APIC */
#define IOREGSEL (0x00/sizeof(uint32_t))
#define IOWIN (0x10/sizeof(uint32_t))
#define IOREGSEL (0x00 / sizeof(uint32_t))
#define IOWIN (0x10 / sizeof(uint32_t))
 
#define IOAPICID 0x00
#define IOAPICVER 0x01
/branches/tracing/kernel/arch/ia32/include/atomic.h
41,17 → 41,17
 
static inline void atomic_inc(atomic_t *val) {
#ifdef CONFIG_SMP
asm volatile ("lock incl %0\n" : "=m" (val->count));
asm volatile ("lock incl %0\n" : "+m" (val->count));
#else
asm volatile ("incl %0\n" : "=m" (val->count));
asm volatile ("incl %0\n" : "+m" (val->count));
#endif /* CONFIG_SMP */
}
 
static inline void atomic_dec(atomic_t *val) {
#ifdef CONFIG_SMP
asm volatile ("lock decl %0\n" : "=m" (val->count));
asm volatile ("lock decl %0\n" : "+m" (val->count));
#else
asm volatile ("decl %0\n" : "=m" (val->count));
asm volatile ("decl %0\n" : "+m" (val->count));
#endif /* CONFIG_SMP */
}
 
61,7 → 61,7
 
asm volatile (
"lock xaddl %1, %0\n"
: "=m" (val->count), "+r" (r)
: "+m" (val->count), "+r" (r)
);
 
return r;
73,14 → 73,14
asm volatile (
"lock xaddl %1, %0\n"
: "=m" (val->count), "+r"(r)
: "+m" (val->count), "+r"(r)
);
return r;
}
 
#define atomic_preinc(val) (atomic_postinc(val)+1)
#define atomic_predec(val) (atomic_postdec(val)-1)
#define atomic_preinc(val) (atomic_postinc(val) + 1)
#define atomic_predec(val) (atomic_postdec(val) - 1)
 
static inline uint32_t test_and_set(atomic_t *val) {
uint32_t v;
88,7 → 88,7
asm volatile (
"movl $1, %0\n"
"xchgl %0, %1\n"
: "=r" (v),"=m" (val->count)
: "=r" (v),"+m" (val->count)
);
return v;
101,20 → 101,20
 
preemption_disable();
asm volatile (
"0:;"
"0:\n"
#ifdef CONFIG_HT
"pause;" /* Pentium 4's HT love this instruction */
"pause\n" /* Pentium 4's HT love this instruction */
#endif
"mov %0, %1;"
"testl %1, %1;"
"jnz 0b;" /* Lightweight looping on locked spinlock */
"mov %0, %1\n"
"testl %1, %1\n"
"jnz 0b\n" /* lightweight looping on locked spinlock */
"incl %1;" /* now use the atomic operation */
"xchgl %0, %1;"
"testl %1, %1;"
"jnz 0b;"
: "=m"(val->count),"=r"(tmp)
);
"incl %1\n" /* now use the atomic operation */
"xchgl %0, %1\n"
"testl %1, %1\n"
"jnz 0b\n"
: "+m" (val->count), "=r"(tmp)
);
/*
* Prevent critical section code from bleeding out this way up.
*/
/branches/tracing/kernel/arch/ia32/include/mm/page.h
128,6 → 128,8
 
#include <mm/mm.h>
#include <arch/interrupt.h>
#include <arch/types.h>
#include <typedefs.h>
 
/* Page fault error codes. */
 
/branches/tracing/kernel/arch/ia32/include/barrier.h
84,6 → 84,15
# endif
#endif
 
/*
* On ia32, the hardware takes care about instruction and data cache coherence,
* even on SMP systems. We issue a write barrier to be sure that writes
* queueing in the store buffer drain to the memory (even though it would be
* sufficient for them to drain to the D-cache).
*/
#define smc_coherence(a) write_barrier()
#define smc_coherence_block(a, l) write_barrier()
 
#endif
 
/** @}
/branches/tracing/kernel/arch/ia32/Makefile.inc
46,7 → 46,8
#
 
ifeq ($(MACHINE),athlon-xp)
CMN2 = -march=athlon-xp -mmmx -msse -m3dnow
FPU_NO_CFLAGS = -mno-mmx -mno-sse -mno-3dnow
CMN2 = -march=athlon-xp
GCC_CFLAGS += $(CMN2)
ICC_CFLAGS += $(CMN2)
SUNCC_CFLAGS += -xarch=ssea
55,7 → 56,8
CONFIG_HT = n
endif
ifeq ($(MACHINE),athlon-mp)
CMN2 = -march=athlon-mp -mmmx -msse -m3dnow
FPU_NO_CFLAGS = -mno-mmx -mno-sse -mno-3dnow
CMN2 = -march=athlon-mp
GCC_CFLAGS += $(CMN2)
ICC_CFLAGS += $(CMN2)
SUNCC_CFLAGS += xarch=ssea
63,7 → 65,8
CONFIG_HT = n
endif
ifeq ($(MACHINE),pentium3)
CMN2 = -march=pentium3 -mmmx -msse
FPU_NO_CFLAGS = -mno-mmx -mno-sse
CMN2 = -march=pentium3
GCC_CFLAGS += $(CMN2)
ICC_CFLAGS += $(CMN2)
SUNCC_CFLAGS += -xarch=sse
71,7 → 74,8
CONFIG_HT = n
endif
ifeq ($(MACHINE),core)
CMN2 = -march=prescott -mfpmath=sse -mmmx -msse -msse2 -msse3
FPU_NO_CFLAGS = -mno-mmmx -mno-sse -mno-sse2 -mno-sse3
CMN2 = -march=prescott
GCC_CFLAGS += $(CMN2)
ICC_CFLAGS += $(CMN2)
SUNCC_CFLAGS += -xarch=sse3
78,7 → 82,8
DEFS += -DCONFIG_FENCES_P4
endif
ifeq ($(MACHINE),pentium4)
GCC_CFLAGS += -march=pentium4 -mfpmath=sse -mmmx -msse -msse2
FPU_NO_CFLAGS = -mno-mmx -mno-sse -mno-sse2
GCC_CFLAGS += -march=pentium4
ICC_CFLAGS += -march=pentium4
SUNCC_CFLAGS += -xarch=sse2
DEFS += -DCONFIG_FENCES_P4
/branches/tracing/kernel/arch/ia32/src/breakpoint.c
34,7 → 34,7
 
#include <arch/breakpoint.h>
#include <panic.h>
#include <console/klog.h>
#include <print.h>
#include <interrupt.h>
#include <func.h>
 
44,7 → 44,7
ASSERT(istate_from_uspace(istate));
 
(void)istate;
klog_printf("breakpoint exception\n");
printf("breakpoint exception\n");
interrupts_enable();
udebug_breakpoint_event(istate->eip);
}
/branches/tracing/kernel/arch/ia32/src/asm.S
37,6 → 37,8
.global paging_on
.global enable_l_apic_in_msr
.global interrupt_handlers
.global memsetb
.global memsetw
.global memcpy
.global memcpy_from_uspace
.global memcpy_from_uspace_failover_address
44,6 → 46,15
.global memcpy_to_uspace_failover_address
 
 
# Wrapper for generic memsetb
memsetb:
jmp _memsetb
 
# Wrapper for generic memsetw
memsetw:
jmp _memsetw
 
 
#define MEMCPY_DST 4
#define MEMCPY_SRC 8
#define MEMCPY_SIZE 12
/branches/tracing/kernel/arch/ia32/src/debug/panic.s
30,5 → 30,5
.global panic_printf
 
panic_printf:
movl $halt,(%esp) # fake stack to make printf return to halt
movl $halt, (%esp) # fake stack to make printf return to halt
jmp printf
/branches/tracing/kernel/arch/ia32/src/pm.c
112,7 → 112,7
 
void tss_initialize(tss_t *t)
{
memsetb((uintptr_t) t, sizeof(struct tss), 0);
memsetb(t, sizeof(struct tss), 0);
}
 
/*
240,7 → 240,7
preemption_disable();
ipl_t ipl = interrupts_disable();
memsetb((uintptr_t) idt, sizeof(idt), 0);
memsetb(idt, sizeof(idt), 0);
ptr_16_32_t idtr;
idtr.limit = sizeof(idt);
/branches/tracing/kernel/arch/ia32/src/smp/smp.c
160,8 → 160,7
panic("couldn't allocate memory for GDT\n");
 
memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(struct descriptor));
memsetb((uintptr_t)(&gdt_new[TSS_DES]),
sizeof(struct descriptor), 0);
memsetb(&gdt_new[TSS_DES], sizeof(struct descriptor), 0);
protected_ap_gdtr.limit = GDT_ITEMS * sizeof(struct descriptor);
protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new);
gdtr.base = (uintptr_t) gdt_new;
/branches/tracing/kernel/arch/ia32/src/smp/ap.S
45,7 → 45,7
KTEXT=8
KDATA=16
 
# This piece of code is real-mode and is meant to be alligned at 4K boundary.
# This piece of code is real-mode and is meant to be aligned at 4K boundary.
# The requirement for such an alignment comes from MP Specification's STARTUP IPI
# requirements.
 
/branches/tracing/kernel/arch/ia32/src/drivers/ega.c
115,7 → 115,7
return;
 
memcpy((void *) videoram, (void *) (videoram + ROW * 2), (SCREEN - ROW) * 2);
memsetw((uintptr_t) (videoram + (SCREEN - ROW) * 2), ROW, 0x0720);
memsetw(videoram + (SCREEN - ROW) * 2, ROW, 0x0720);
ega_cursor = ega_cursor - ROW;
}