/branches/sparc/usii.simics |
---|
12,21 → 12,21 |
script-branch { |
wait-for-variable machine_defined |
$pcibrd = (create-sunfire-pci-board mac_address = "10:10:10:10:10:14") |
#$pgx64 = (create-sun-pci-pgx64) |
#$gfxcon = (create-std-graphics-console) |
#$keyboard = (create-sun-type5-keyboard) |
#$mouse = (create-sun-type5-mouse) |
$pgx64 = (create-sun-pci-pgx64) |
$gfxcon = (create-std-graphics-console) |
$keyboard = (create-sun-type5-keyboard) |
$mouse = (create-sun-type5-mouse) |
$scsi_bus = (create-std-scsi-bus) |
$system.connect slot2 $pcibrd |
#$pcibrd.connect pci-slot0 $pgx64 |
$pcibrd.connect pci-slot0 $pgx64 |
$pcibrd.connect $scsi_bus |
#$system.connect keyboard $keyboard |
#$system.connect mouse $mouse |
$system.connect keyboard $keyboard |
$system.connect mouse $mouse |
#$gfxcon.connect $pgx64 |
#$gfxcon.connect $keyboard |
#$gfxcon.connect $mouse |
$gfxcon.connect $pgx64 |
$gfxcon.connect $keyboard |
$gfxcon.connect $mouse |
} |
$save_slot2 = "yes" |
107,7 → 107,7 |
$system.set-prom-env boot-command "boot cdrom" |
$system.set-prom-env auto-boot? true |
#$system.set-prom-env "output-device" "screen:r1152x900x76x24" |
$system.set-prom-env "output-device" "screen:r1152x900x76x24" |
@buf = 0; |
@offset = 0; |
/branches/sparc/kernel/kernel.config |
---|
91,6 → 91,9 |
# Framebuffer support |
! [(ARCH=mips32&MACHINE=lgxemul)|(ARCH=mips32&MACHINE=bgxemul)|(ARCH=ia32)|(ARCH=amd64)|(ARCH=arm32)] CONFIG_FB (y/n) |
# Output to Simics console |
! [ARCH=sparc64] CONFIG_SIMICS_OUTPUT (n/y) |
# Framebuffer width |
@ "640" |
@ "800" |
/branches/sparc/kernel/Makefile |
---|
150,6 → 150,12 |
endif |
endif |
ifeq ($(CONFIG_SIMICS_OUTPUT),y) |
ifeq ($(ARCH),sparc64) |
DEFS += -DCONFIG_SIMICS_OUTPUT |
endif |
endif |
ifeq ($(CONFIG_UDEBUG),y) |
DEFS += -DCONFIG_UDEBUG |
endif |
/branches/sparc/kernel/arch/sparc64/include/mm/mmu.h |
---|
54,7 → 54,12 |
#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
#if defined (US3) |
#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ |
#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ |
#endif |
/* D-MMU ASIs. */ |
#define ASI_DMMU 0x58 |
#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
75,6 → 80,11 |
#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
#if defined (US3) |
#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ |
#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ |
#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ |
#endif |
#ifndef __ASM__ |
/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h |
---|
41,7 → 41,7 |
#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
#endif |
/** DT16 is the only of the three DMMU caches that can hold locked entries. */ |
/** DT16 is the only of the three DMMUs that can hold locked entries. */ |
#if defined (US3) |
#define DTLB_MAX_LOCKED_ENTRIES 16 |
#endif |
640,4 → 640,4 |
#endif |
/** @} |
*/ |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/tsb.h |
---|
107,6 → 107,55 |
asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); |
} |
#if defined (US3) |
/** Write DTSB Primary Extension register. |
* |
* @param v New content of the DTSB Primary Extension register. |
*/ |
static inline void dtsb_primary_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v); |
} |
/** Write DTSB Secondary Extension register. |
* |
* @param v New content of the DTSB Secondary Extension register. |
*/ |
static inline void dtsb_secondary_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v); |
} |
/** Write DTSB Nucleus Extension register. |
* |
* @param v New content of the DTSB Nucleus Extension register. |
*/ |
static inline void dtsb_nucleus_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v); |
} |
/** Write ITSB Primary Extension register. |
* |
* @param v New content of the ITSB Primary Extension register. |
*/ |
static inline void itsb_primary_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v); |
} |
/** Write ITSB Nucleus Extension register. |
* |
* @param v New content of the ITSB Nucleus Extension register. |
*/ |
static inline void itsb_nucleus_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v); |
} |
#endif |
/* Forward declarations. */ |
struct as; |
struct pte; |
/branches/sparc/kernel/arch/sparc64/src/smp/ipi.c |
---|
100,6 → 100,8 |
if (status & INTR_DISPATCH_STATUS_BUSY) |
panic("Interrupt Dispatch Status busy bit set\n"); |
ASSERT(!(pstate_read() & PSTATE_IE_BIT)); |
do { |
set_intr_w_data(func); |
asi_u64_write(ASI_INTR_W, |
/branches/sparc/kernel/arch/sparc64/src/ddi/ddi.c |
---|
41,7 → 41,7 |
* Interrupts are disabled and task is locked. |
* |
* @param task Task. |
* @param ioaddr Startign I/O space address. |
* @param ioaddr Starting I/O space address. |
* @param size Size of the enabled I/O range. |
* |
* @return 0 on success or an error code from errno.h. |
/branches/sparc/kernel/arch/sparc64/src/sparc64.c |
---|
87,9 → 87,12 |
* But we only create 128 buckets. |
*/ |
irq_init(1 << 11, 128); |
#if defined (CONFIG_SIMICS_OUTPUT) |
simics_output_init(); |
//standalone_sparc64_console_init(); |
#else |
standalone_sparc64_console_init(); |
#endif |
} |
} |
/branches/sparc/kernel/arch/sparc64/src/trap/interrupt.c |
---|
67,8 → 67,12 |
*/ |
void interrupt(int n, istate_t *istate) |
{ |
uint64_t status; |
uint64_t intrcv; |
uint64_t data0; |
status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
if (status & (!INTR_DISPATCH_STATUS_BUSY)) |
panic("Interrupt Dispatch Status busy bit not set\n"); |
intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); |
#if defined (US) |
/branches/sparc/kernel/arch/sparc64/src/mm/tlb.c |
---|
103,7 → 103,7 |
pg.address = page; |
fr.address = frame; |
tag.value = ASID_KERNEL; |
tag.context = ASID_KERNEL; |
tag.vpn = pg.vpn; |
dtlb_tag_access_write(tag.value); |
467,9 → 467,16 |
sfsr.value = dtlb_sfsr_read(); |
sfar = dtlb_sfar_read(); |
#if defined (US) |
printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
"fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
sfsr.ow, sfsr.fv); |
#elif defined (US3) |
printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
"fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
sfsr.ow, sfsr.fv); |
#endif |
printf("DTLB SFAR: address=%p\n", sfar); |
dtlb_sfsr_write(0); |
618,4 → 625,4 |
} |
/** @} |
*/ |
*/ |
/branches/sparc/kernel/arch/sparc64/src/mm/as.c |
---|
164,7 → 164,25 |
itsb_base_write(tsb_base.value); |
tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
dtsb_base_write(tsb_base.value); |
#if defined (US3) |
/* |
* Clear the extension registers. |
* In HelenOS, primary and secondary context registers contain |
* equal values and kernel misses (context 0, ie. the nucleus context) |
* are excluded from the TSB miss handler, so it makes no sense |
* to have separate TSBs for primary, secondary and nucleus contexts. |
* Clearing the extension registers will ensure that the value of the |
* TSB Base register will be used as an address of TSB, making the code |
* compatible with the US port. |
*/ |
itsb_primary_extension_write(0); |
itsb_nucleus_extension_write(0); |
dtsb_primary_extension_write(0); |
dtsb_secondary_extension_write(0); |
dtsb_nucleus_extension_write(0); |
#endif |
#endif |
} |
/** Perform sparc64-specific tasks when an address space is removed from the |
/branches/sparc/uspace/app/init/init.c |
---|
105,7 → 105,7 |
} |
// FIXME: spawn("/srv/pci"); |
//spawn("/srv/fb"); |
spawn("/srv/fb"); |
spawn("/srv/kbd"); |
spawn("/srv/console"); |