/branches/sparc/kernel/arch/sparc64/include/trap/exception.h |
---|
37,6 → 37,7 |
#define KERN_sparc64_EXCEPTION_H_ |
#define TT_INSTRUCTION_ACCESS_EXCEPTION 0x08 |
#define TT_INSTRUCTION_ACCESS_MMU_MISS 0x09 |
#define TT_INSTRUCTION_ACCESS_ERROR 0x0a |
#define TT_IAE_UNAUTH_ACCESS 0x0b |
#define TT_IAE_NFO_PAGE 0x0c |
54,6 → 55,7 |
#define TT_TAG_OVERFLOW 0x23 |
#define TT_DIVISION_BY_ZERO 0x28 |
#define TT_DATA_ACCESS_EXCEPTION 0x30 |
#define TT_DATA_ACCESS_MMU_MISS 0x31 |
#define TT_DATA_ACCESS_ERROR 0x32 |
#define TT_MEM_ADDRESS_NOT_ALIGNED 0x34 |
#define TT_LDDF_MEM_ADDRESS_NOT_ALIGNED 0x35 |
/branches/sparc/kernel/arch/sparc64/src/trap/sun4v/trap_table.S |
---|
67,6 → 67,12 |
instruction_access_exception_tl0: |
PREEMPTIBLE_HANDLER instruction_access_exception |
/* TT = 0x09, TL = 0, instruction_access_mmu_miss */ |
.org trap_table + TT_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE |
.global instruction_access_mmu_miss_handler_tl0 |
ba fast_instruction_access_mmu_miss_handler_tl0 |
nop |
/* TT = 0x0a, TL = 0, instruction_access_error */ |
.org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE |
.global instruction_access_error_tl0 |
176,6 → 182,13 |
data_access_exception_tl0: |
PREEMPTIBLE_HANDLER data_access_exception |
/* TT = 0x31, TL = 0, data_access_mmu_miss */ |
.org trap_table + TT_DATA_ACCESS_MMU_MISS*ENTRY_SIZE |
.global data_access_mmu_miss_tl0 |
data_access_mmu_miss_tl0: |
ba fast_data_access_mmu_miss_handler_tl0 |
nop |
/* TT = 0x32, TL = 0, data_access_error */ |
.org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE |
.global data_access_error_tl0 |
396,6 → 409,13 |
wrpr %g0, 1, %tl |
PREEMPTIBLE_HANDLER instruction_access_exception |
/* TT = 0x09, TL > 0, instruction_access_mmu_miss */ |
.org trap_table + (TT_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE |
.global instruction_access_mmu_miss_handler_tl1 |
wrpr %g0, 1, %tl |
ba fast_instruction_access_mmu_miss_handler_tl0 |
nop |
/* TT = 0x0a, TL > 0, instruction_access_error */ |
.org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE |
.global instruction_access_error_tl1 |
473,6 → 493,14 |
wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
PREEMPTIBLE_HANDLER data_access_exception*/ |
/* TT = 0x31, TL > 0, data_access_mmu_miss */ |
.org trap_table + (TT_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE |
.global data_access_mmu_miss_tl1 |
data_access_mmu_miss_tl1: |
ba fast_data_access_mmu_miss_handler_tl1 |
nop |
/* TT = 0x32, TL > 0, data_access_error */ |
.org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE |
.global data_access_error_tl1 |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/as.c |
---|
66,7 → 66,7 |
int order = fnzb32( |
(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
uintptr_t tsb = (uintptr_t) frame_alloc(order, flags); |
if (!tsb) |
return -1; |
77,8 → 77,9 |
as->arch.tsb_description.pgsize_mask = 1 << PAGESIZE_8K; |
as->arch.tsb_description.tsb_base = tsb; |
as->arch.tsb_description.reserved = 0; |
as->arch.tsb_description.context = 0; |
memsetb((void *) as->arch.tsb_description.tsb_base, |
memsetb((void *) PA2KA(as->arch.tsb_description.tsb_base), |
TSB_ENTRY_COUNT * sizeof(tsb_entry_t), 0); |
#endif |
return 0; |
88,7 → 89,7 |
{ |
#ifdef CONFIG_TSB |
count_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
frame_free(KA2PA((uintptr_t) as->arch.tsb_description.tsb_base)); |
frame_free((uintptr_t) as->arch.tsb_description.tsb_base); |
return cnt; |
#else |
return 0; |
99,7 → 100,6 |
{ |
#ifdef CONFIG_TSB |
tsb_invalidate(as, 0, (count_t) -1); |
as->arch.tsb_description.context = as->asid; |
#endif |
return 0; |
} |
119,7 → 119,7 |
uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
ASSERT(as->arch.tsb_description.tsb_base); |
uintptr_t tsb = as->arch.tsb_description.tsb_base; |
uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); |
if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
/* |
131,7 → 131,7 |
dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); |
} |
__hypercall_fast2(MMU_TSB_CTX0, 1, as->arch.tsb_description.tsb_base); |
__hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description))); |
#endif |
} |
156,7 → 156,7 |
ASSERT(as->arch.tsb_description.tsb_base); |
uintptr_t tsb = as->arch.tsb_description.tsb_base; |
uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); |
if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
/* |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/tsb.c |
---|
71,7 → 71,7 |
cnt = pages; |
for (i = 0; i < cnt; i++) { |
((tsb_entry_t *) as->arch.tsb_description.tsb_base)[ |
((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[ |
(i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false; |
} |
} |
89,7 → 89,7 |
as = t->as; |
entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; |
ASSERT(entry < TSB_ENTRY_COUNT); |
tsb = &((tsb_entry_t *) as->arch.tsb_description.tsb_base)[entry]; |
tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry]; |
/* |
* We use write barriers to make sure that the TSB load |
101,7 → 101,6 |
write_barrier(); |
tsb->tag.context = as->asid; |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |
135,7 → 134,7 |
as = t->as; |
entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; |
ASSERT(entry < TSB_ENTRY_COUNT); |
tsb = &((tsb_entry_t *) as->arch.tsb_description.tsb_base)[entry]; |
tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry]; |
/* |
* We use write barriers to make sure that the TSB load |
147,7 → 146,6 |
write_barrier(); |
tsb->tag.context = as->asid; |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |